Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9760664 | Validating variation of timing constraint measurements | Sachin Gupta, Vasant Rao, Suriya T. Skariah, James D. Warnock | 2017-09-12 |
| 9760665 | Validating variation of timing constraint measurements | Sachin Gupta, Vasant Rao, Suriya T. Skariah, James D. Warnock | 2017-09-12 |
| 9323875 | Dynamically determining number of simulations required for characterizing intra-circuit incongruent variations | Peter A. Habitz, Amol A. Joshi, Amith Singhee, Wangyang Zhang | 2016-04-26 |
| 7275226 | Method of performing latch up check on an integrated circuit design | Henry A. Bonges, III, David C. Reynolds | 2007-09-25 |