Issued Patents All Time
Showing 1–25 of 88 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12417925 | Method of conductive material deposition | Hirokazu Aizawa, Kai-Hung Yu, Nicholas Joy, Yusuke Yoshida | 2025-09-16 |
| 12336274 | Self-aligned method for vertical recess for 3D device integration | Jeffrey Smith, Daniel Chanemougame, Lars Liebmann, Paul Gutwin, Subhadeep Kal +1 more | 2025-06-17 |
| 12284820 | Dual metal wrap-around contacts for semiconductor devices | Hiroaki Niimi, Takahiro Hakamata | 2025-04-22 |
| 12020990 | Method for threshold voltage tuning through selective deposition of high-k metal gate (HKMG) film stacks | Jeffrey Smith, Lars Liebmann, Daniel Chanemougame, Mark I. Gardner, H. Jim Fulford +1 more | 2024-06-25 |
| 11901360 | Architecture design and process for manufacturing monolithically integrated 3D CMOS logic and memory | Lars Liebmann, Jeffrey Smith, Anton J. deVilliers | 2024-02-13 |
| 11804376 | Method for mitigating lateral film growth in area selective deposition | — | 2023-10-31 |
| 11769677 | Substrate processing tool with integrated metrology and method of using | Robert D. Clark | 2023-09-26 |
| 11705369 | Fully self-aligned via with selective bilayer dielectric regrowth | Jeffrey Smith | 2023-07-18 |
| 11700778 | Method for controlling the forming voltage in resistive random access memory devices | Steven P. Consiglio, Cory Wajda, Takaaki Tsunomura, Takashi Ando, Paul C. Jamison +3 more | 2023-07-11 |
| 11676968 | Coaxial contacts for 3D logic and memory | Lars Liebmann, Jeffrey Smith, Anton J. deVilliers | 2023-06-13 |
| 11658068 | Method of selective deposition for forming fully self-aligned vias | — | 2023-05-23 |
| 11658066 | Method for reducing lateral film formation in area selective deposition | — | 2023-05-23 |
| 11646227 | Method of forming a semiconductor device with air gaps for low capacitance interconnects | — | 2023-05-09 |
| 11621190 | Method for filling recessed features in semiconductor devices with a low-resistivity metal | Kai-Hung Yu, David L. O'Meara, Nicholas Joy, Gyanaranjan Pattanaik, Robert D. Clark +3 more | 2023-04-04 |
| 11616053 | Method to vertically route a logic cell incorporating stacked transistors in a three dimensional logic device | Jeffrey Smith, Anton J. deVilliers | 2023-03-28 |
| 11616020 | Power distribution network for 3D logic and memory | Lars Liebmann, Jeffrey Smith, Anton J. deVilliers | 2023-03-28 |
| 11594451 | Platform and method of operating for integrated end-to-end fully self-aligned interconnect process | Robert D. Clark, Kai-Hung Yu | 2023-02-28 |
| 11532517 | Localized etch stop layer | Yun Han, Andrew Metz, Xinghua Sun, David L. O'Meara, Henan Zhang +1 more | 2022-12-20 |
| 11456212 | Platform and method of operating for integrated end-to-end fully self-aligned interconnect process | Robert D. Clark, Kai-Hung Yu | 2022-09-27 |
| 11443949 | Method of selectively forming metal silicides for semiconductor devices | — | 2022-09-13 |
| 11443953 | Method for forming and using stress-tuned silicon oxide films in semiconductor device patterning | Anton J. deVilliers, Gerrit J. Leusink | 2022-09-13 |
| 11444082 | Semiconductor apparatus having stacked gates and method of manufacture thereof | Jeffrey Smith, Anton J. deVilliers, Subhadeep Kal, Gerrit J. Leusink | 2022-09-13 |
| 11398379 | Platform and method of operating for integrated end-to-end self-aligned multi-patterning process | Robert D. Clark, Richard A. Farrell, Angelique Raley, Sophie Thibaut | 2022-07-26 |
| 11374101 | Dual metal wrap-around contacts for semiconductor devices | Hiroaki Niimi, Takahiro Hakamata | 2022-06-28 |
| 11335599 | Self-aligned contacts for 3D logic and memory | Lars Liebmann, Jeffrey Smith, Anton J. deVilliers | 2022-05-17 |