Issued Patents All Time
Showing 25 most recent of 107 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12414367 | Tapered device for lateral gate all around devices | Lars Liebmann, Daniel Chanemougame, Paul Gutwin | 2025-09-09 |
| 12354991 | Replacement buried power rail in backside power delivery | Hoyoung Kang, Lars Liebmann, Anton J. deVilliers, Daniel Chanemougame | 2025-07-08 |
| 12336274 | Self-aligned method for vertical recess for 3D device integration | Daniel Chanemougame, Lars Liebmann, Paul Gutwin, Subhadeep Kal, Kandabara Tapily +1 more | 2025-06-17 |
| 12237333 | Power wall integration for multiple stacked devices | Daniel Chanemougame, Lars Liebmann | 2025-02-25 |
| 12224281 | Interdigitated device stack | Lars Liebmann, Daniel Chanemougame, Paul Gutwin, Brian Tracy Cline, Xiaoqing Xu +1 more | 2025-02-11 |
| 12218066 | Monolithic formation of a set of interconnects below active devices | Daniel Chanemougame, Lars Liebmann | 2025-02-04 |
| 12218135 | Wiring in diffusion breaks in an integrated circuit | Lars Liebmann, Daniel Chanemougame, Paul Gutwin | 2025-02-04 |
| 12176293 | Inter-tier power delivery network (PDN) for dense gate-on-gate 3D logic integration | Lars Liebmann, Daniel Chanemougame, Paul Gutwin, Brian Tracy Cline, Xiaoqing Xu +1 more | 2024-12-24 |
| 12087640 | High density logic formation using multi-dimensional laser annealing | H. Jim Fulford, Mark I. Gardner, Lars Liebmann, Daniel Chanemougame | 2024-09-10 |
| 12051638 | Integrated high efficiency transistor cooling | Daniel Chanemougame, Lars Liebmann, Paul Gutwin | 2024-07-30 |
| 12040271 | Power delivery network for CFET with buried power rails | Lars Liebmann, Daniel Chanemougame, Anton J. deVilliers | 2024-07-16 |
| 12020990 | Method for threshold voltage tuning through selective deposition of high-k metal gate (HKMG) film stacks | Kandabara Tapily, Lars Liebmann, Daniel Chanemougame, Mark I. Gardner, H. Jim Fulford +1 more | 2024-06-25 |
| 12014984 | Method of manufacturing a semiconductor apparatus having stacked devices | Lars Liebmann, Anton J. deVilliers | 2024-06-18 |
| 12002862 | Inter-level handshake for dense 3D logic integration | Lars Liebmann, Daniel Chanemougame, Paul Gutwin | 2024-06-04 |
| 11961802 | Power-tap pass-through to connect a buried power rail to front-side power distribution network | Lars Liebmann, Daniel Chanemougame, Paul Gutwin | 2024-04-16 |
| 11923364 | Double cross-couple for two-row flip-flop using CFET | Lars Liebmann, Daniel Chanemougame, Paul Gutwin | 2024-03-05 |
| 11901360 | Architecture design and process for manufacturing monolithically integrated 3D CMOS logic and memory | Lars Liebmann, Anton J. deVilliers, Kandabara Tapily | 2024-02-13 |
| 11841617 | Method of forming a narrow trench | Anton J. deVilliers, Jodi Grzeskowiak, Daniel Fulford, Richard A. Farrell | 2023-12-12 |
| 11830852 | Multi-tier backside power delivery network for dense gate-on-gate 3D logic | Lars Liebmann, Daniel Chanemougame, Paul Gutwin, Brian Tracy Cline, Xiaoqing Xu +1 more | 2023-11-28 |
| 11791271 | Monolithic formation of a set of interconnects below active devices | Daniel Chanemougame, Lars Liebmann | 2023-10-17 |
| 11764113 | Method of 3D logic fabrication to sequentially decrease processing temperature and maintain material thermal thresholds | Daniel Chanemougame, Lars Liebmann, Paul Gutwin, Robert D. Clark, Anton J. deVilliers | 2023-09-19 |
| 11764266 | Three-dimensional semiconductor device | Lars Liebmann, Daniel Chanemougame, Paul Gutwin | 2023-09-19 |
| 11742241 | ALD (atomic layer deposition) liner for via profile control and related applications | Xinghua Sun, Yen-Tien Lu, Angelique Raley, David L. O'Meara | 2023-08-29 |
| 11735525 | Power delivery network for CFET with buried power rails | Lars Liebmann, Anton J. deVilliers, Daniel Chanemougame | 2023-08-22 |
| 11705369 | Fully self-aligned via with selective bilayer dielectric regrowth | Kandabara Tapily | 2023-07-18 |