Issued Patents All Time
Showing 1–24 of 24 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8865571 | Dislocation engineering using a scanned laser | Xiao Hu Liu, Anita Madan, Klaus W. Schwarz, J. Campbell Scott | 2014-10-21 |
| 8865572 | Dislocation engineering using a scanned laser | Xiao Hu Liu, Anita Madan, Klaus W. Schwarz, J. Campbell Scott | 2014-10-21 |
| 8716081 | Capacitor top plate over source/drain to form a 1T memory device | Lee-Wee Teo, Yong Meng Lee, Zhao Lun, Shyue Seng Tan, Jeffrey Chee +2 more | 2014-05-06 |
| 8624329 | Spacer-less low-K dielectric processes | Yong Meng Lee, Young Way Teh, Wenhe Lin, Khee Yong Lim, Wee Leng Tan +3 more | 2014-01-07 |
| 8274115 | Hybrid orientation substrate with stress layer | Lee-Wee Teo, Johnny Widodo, Shyue Seng Tan, Shailendra Mishra, Zhao Lun +2 more | 2012-09-25 |
| 8198194 | Methods of forming p-channel field effect transistors having SiGe source/drain regions | Jong-ho Yang, Hyung-Rae Lee, Jin-Ping Han, Henry K. Utomo, Thomas W. Dyer | 2012-06-12 |
| 8178417 | Method of forming shallow trench isolation structures for integrated circuits | Shailendra Mishra, James Yong Meng Lee, Zhao Lun, Wen Zhi Gao, Huang Liu +2 more | 2012-05-15 |
| 8143651 | Nested and isolated transistors with reduced impedance difference | Johnny Widodo, Liang-Choo Hsia, James Yong Meng Lee, Wen Zhi Gao, Zhao Lun +5 more | 2012-03-27 |
| 8138066 | Dislocation engineering using a scanned laser | Xiao Hu Liu, Anita Madan, Klaus W. Schwarz, J. Campbell Scott | 2012-03-20 |
| 8053327 | Method of manufacture of an integrated circuit system with self-aligned isolation structures | Shailendra Mishra, Lee-Wee Teo, Yong Meng Lee, Zhao Lun, Shyue Seng Tan +2 more | 2011-11-08 |
| 7999325 | Method to remove spacer after salicidation to enhance contact etch stop liner stress on MOS | Young Way Teh, Yong Meng Lee, Wenhe Lin, Khee Yong Lim, Wee Leng Tan +3 more | 2011-08-16 |
| 7999300 | Memory cell structure and method for fabrication thereof | Zhao Lun, James Yong Meng Lee, Lee-Wee Teo, Shyue Seng Tan, Johnny Widodo +2 more | 2011-08-16 |
| 7977185 | Method and apparatus for post silicide spacer removal | Brian J. Greene, Yong Meng Lee, Wenhe Lin, Siddhartha Panda, Kern Rim +1 more | 2011-07-12 |
| 7955936 | Semiconductor fabrication process including an SiGe rework method | Yong Siang Tan, Jin-Ping Han, Henry K. Utomo, Judson R. Holt, Eric C. Harley +2 more | 2011-06-07 |
| 7935593 | Stress optimization in dual embedded epitaxially grown semiconductor processing | Jong-ho Yang, Jin-Ping Han, Henry K. Utomo | 2011-05-03 |
| 7932178 | Integrated circuit having a plurality of MOSFET devices | Lee-Wee Teo, Yong Meng Lee, Jeffrey Chee, Shyue Seng Tan, Johnny Widodo +2 more | 2011-04-26 |
| 7838372 | Methods of manufacturing semiconductor devices and structures thereof | Jin-Ping Han, Jong-ho Yang, Henry K. Utomo | 2010-11-23 |
| 7795680 | Integrated circuit system employing selective epitaxial growth technology | Huang Liu, Alex See, James Yong Meng Lee, Johnny Widodo, Wenzhi Gao +3 more | 2010-09-14 |
| 7767577 | Nested and isolated transistors with reduced impedance difference | Johnny Widodo, Liang-Choo Hsia, James Yong Meng Lee, Wen Zhi Gao, Zhao Lun +5 more | 2010-08-03 |
| 7615427 | Spacer-less low-k dielectric processes | Yong Meng Lee, Young Way Teh, Wenhe Lin, Khee Yong Lim, Wee Leng Tan +3 more | 2009-11-10 |
| 7445978 | Method to remove spacer after salicidation to enhance contact etch stop liner stress on MOS | Young Way Teh, Yong Meng Lee, Wenhe Lin, Khee Yong Lim, Wee Leng Tan +3 more | 2008-11-04 |
| 7256084 | Composite stress spacer | Khee Yong Lim, Wenhe Lin, Yong Meng Lee, Liang-Choo Hsia, Young Way Teh +3 more | 2007-08-14 |
| 6653227 | Method of cobalt silicidation using an oxide-Titanium interlayer | Beichao Zhang, Eng Hua Lim, Arthur Ang, Hai Jiang Peng, Charles Lin | 2003-11-25 |
| 6383922 | Thermal stability improvement of CoSi2 film by stuffing in titanium | Bei Chao Zhang, Eng Hua Lim, Mei Sheng Zhou, Peter Chew, Arthur Ang | 2002-05-07 |