Issued Patents All Time
Showing 1–25 of 26 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9627219 | CMP wafer edge control of dielectric | Lei Wang, Xuesong Rao, Alex See | 2017-04-18 |
| 9620418 | Methods for fabricating integrated circuits with improved active regions | Liang Li, Lian Choo Goh, Yung Fu Chong, Fangyue Liu, Alex See | 2017-04-11 |
| 9520371 | Planar passivation for pads | Benfu Lin, Wanbing Yi, Alex See, Juan Boon Tan | 2016-12-13 |
| 9511474 | CMP head structure with retaining ring | Benfu Lin, Alex See | 2016-12-06 |
| 9511470 | CMP head structure with retaining ring | Benfu Lin, Lei Wang, Xuesong Rao, Alex See | 2016-12-06 |
| 9443761 | Methods for fabricating integrated circuits having device contacts | Wei Shao, Fan Zhang, Wuping Liu, Vish Srinivasan, Juan Boon Tan | 2016-09-13 |
| 9437547 | Through silicon vias | Benfu Lin, Hong-Chi Yu, Lup San Leong, Alex See | 2016-09-06 |
| 9349654 | Isolation for embedded devices | Liang Li, Xuesong Rao, Martina Damayanti, Alex See, Yoke Leng Lim | 2016-05-24 |
| 9287197 | Through silicon vias | Benfu Lin, Hong-Chi Yu, Lup San Leong, Alex See | 2016-03-15 |
| 9242341 | CMP head structure | Benfu Lin, Alex See | 2016-01-26 |
| 9242338 | CMP head structure | Benfu Lin, Lei Wang, Xuesong Rao, Alex See | 2016-01-26 |
| 9202746 | Integrated circuits with improved gap fill dielectric and methods for fabricating same | Lei Wang, Lup San Leong, Alex See | 2015-12-01 |
| 9153473 | Wafer processing | Liang Li | 2015-10-06 |
| 8354347 | Method of forming high-k dielectric stop layer for contact hole opening | Jianhui Ye, Huang Liu, Alex See, Chun Hui Low, Chim Seng Seet +2 more | 2013-01-15 |
| 8264088 | Planarized passivation layer for semiconductor devices | Sin Leng Lim, In-Ki Kim, Jong Sung Park, Min Hwan Kim | 2012-09-11 |
| 8013372 | Integrated circuit including a stressed dielectric layer with stable stress | Huang Liu, Jeff Shu, Luona Goh | 2011-09-06 |
| 7998831 | Planarized passivation layer for semiconductor devices | Sin Leng Lim, In-Ki Kim, Jong Sung Park, Min Hwan Kim | 2011-08-16 |
| 7960283 | Method for reducing silicide defects in integrated circuits | Jeff Jianhui Ye, Huang Liu, Alex See, Hai Cong, Hui Peng Koh +2 more | 2011-06-14 |
| 7892900 | Integrated circuit system employing sacrificial spacers | Huang Liu, Hai Cong, Alex See, Hui Peng Koh, Meisheng Zhou | 2011-02-22 |
| 7855143 | Interconnect capping layer and method of fabrication | Huang Liu, Bangun Indajang | 2010-12-21 |
| 7790617 | Formation of metal silicide layer over copper interconnect for reliability enhancement | Yeow Kheng Lim, Liang-Choo Hsia, Jyoti Gupta, Chim Seng Seet, Hao Zhang | 2010-09-07 |
| 7745320 | Method for reducing silicide defects in integrated circuits | Jeff Jianhui Ye, Huang Liu, Alex See, Hai Cong, Hui Peng Koh +2 more | 2010-06-29 |
| 7566656 | Method and apparatus for providing void structures | Huang Liu, Johnny Widodo | 2009-07-28 |
| 7332422 | Method for CuO reduction by using two step nitrogen oxygen and reducing plasma treatment | Loh Nah Luona Goh, Liang-Choo Hsia | 2008-02-19 |
| 7271110 | High density plasma and bias RF power process to make stable FSG with less free F and SiN with less H to enhance the FSG/SiN integration reliability | Liang-Choo Hsia | 2007-09-18 |