Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9368453 | Overlay mark dependent dummy fill to mitigate gate height variation | Guoxiang Ning, Chan Seob Cho, Paul Ackmann, Jung-Yu Hsieh | 2016-06-14 |
| 9252061 | Overlay mark dependent dummy fill to mitigate gate height variation | Guoxiang Ning, Chan Seob Cho, Paul Ackmann, Jung-Yu Hsieh | 2016-02-02 |
| 8940641 | Methods for fabricating integrated circuits with improved patterning schemes | Xiang Hu, Taejoon Han | 2015-01-27 |
| 8911920 | Methods for fabricating EUV masks and methods for fabricating integrated circuits using such EUV masks | Sudharshanan Raghunathan, Pawitter S. Mangat | 2014-12-16 |
| 8624329 | Spacer-less low-K dielectric processes | Yong Meng Lee, Young Way Teh, Chung Woh Lai, Wenhe Lin, Khee Yong Lim +3 more | 2014-01-07 |
| 7999325 | Method to remove spacer after salicidation to enhance contact etch stop liner stress on MOS | Young Way Teh, Yong Meng Lee, Chung Woh Lai, Wenhe Lin, Khee Yong Lim +3 more | 2011-08-16 |
| 7960283 | Method for reducing silicide defects in integrated circuits | Jeff Jianhui Ye, Huang Liu, Alex See, Wei Lu, Hai Cong +2 more | 2011-06-14 |
| 7892900 | Integrated circuit system employing sacrificial spacers | Huang Liu, Wei Lu, Hai Cong, Alex See, Meisheng Zhou | 2011-02-22 |
| 7745320 | Method for reducing silicide defects in integrated circuits | Jeff Jianhui Ye, Huang Liu, Alex See, Wei Lu, Hai Cong +2 more | 2010-06-29 |
| 7615427 | Spacer-less low-k dielectric processes | Yong Meng Lee, Young Way Teh, Chung Woh Lai, Wenhe Lin, Khee Yong Lim +3 more | 2009-11-10 |
| 7445978 | Method to remove spacer after salicidation to enhance contact etch stop liner stress on MOS | Young Way Teh, Yong Meng Lee, Chung Woh Lai, Wenhe Lin, Khee Yong Lim +3 more | 2008-11-04 |
| 7256084 | Composite stress spacer | Khee Yong Lim, Wenhe Lin, Chung Woh Lai, Yong Meng Lee, Liang-Choo Hsia +3 more | 2007-08-14 |