Issued Patents All Time
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8999863 | Stress liner for stress engineering | Jae Gon Lee, Jingze Tian, Shyue Seng Tan, Wei-Chung Lu, Elgin Quek | 2015-04-07 |
| 8013372 | Integrated circuit including a stressed dielectric layer with stable stress | Huang Liu, Jeff Shu, Wei Lu | 2011-09-06 |
| 7224060 | Integrated circuit with protective moat | Fan Zhang, Kho Liep Chok, Tae Jong Lee, Xiaomei Bu, Meng Luo +4 more | 2007-05-29 |
| 7078333 | Method to improve adhesion of dielectric films in damascene interconnects | Simon Chooi, Siew Lok Toh, Tong Earn Tay | 2006-07-18 |
| 6797605 | Method to improve adhesion of dielectric films in damascene interconnects | Simon Chooi, Siew Lok Toh, Tong Earn Tay | 2004-09-28 |