Issued Patents All Time
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12393518 | Deterministic mixed latency cache | — | 2025-08-19 |
| 12306754 | Method and apparatus for increasing memory level parallelism by reducing miss status holding register allocation in caches | Jagadish B. Kotra, John Kalamatianos, Paul James Moyer, Nicholas Dean Lance, Sriram Srinivasan +1 more | 2025-05-20 |
| 12266585 | Arrangement and thermal management of 3D stacked dies | John Wuu, Samuel D. Naffziger, Milind S. Bhagavat, Kaushik Mysore, Brett P. Wilkerson | 2025-04-01 |
| 12009047 | Systems and methods for continuous wordline monitoring | — | 2024-06-11 |
| 11782897 | System and method for multiplexer tree indexing | Steven R. Havlir | 2023-10-10 |
| 11776599 | Encoded enable clock gaters | — | 2023-10-03 |
| 11308057 | System and method for multiplexer tree indexing | Steven R. Havlir | 2022-04-19 |
| 11189540 | Arrangement and thermal management of 3D stacked dies | John Wuu, Samuel D. Naffziger, Milind S. Bhagavat, Kaushik Mysore, Brett P. Wilkerson | 2021-11-30 |
| 11164807 | Arrangement and thermal management of 3D stacked dies | John Wuu, Samuel D. Naffziger, Milind S. Bhagavat, Kaushik Mysore, Brett P. Wilkerson | 2021-11-02 |
| 10509752 | Configuration of multi-die modules with through-silicon vias | Russell Schreiber, John Wuu, Michael Kevin Ciraula | 2019-12-17 |
| 10431517 | Arrangement and thermal management of 3D stacked dies | John Wuu, Samuel D. Naffziger, Milind S. Bhagavat, Kaushik Mysore, Brett P. Wilkerson | 2019-10-01 |
| 10333500 | Self-gating pulsed flip-flop | David S. Vickers | 2019-06-25 |
| 10311191 | Memory including side-car arrays with irregular sized entries | John Wuu, Ryan Alan Selby | 2019-06-04 |