Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method and apparatus for increasing memory level parallelism by reducing miss status holding register allocation in caches

Method and apparatus for increasing memory level parallelism by reducing miss status holding register allocation in caches

US Patent 12306754 · Granted May 20, 2025

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Storing indications of cleared cache lines2025
Storing indications of cleared cache lines2025
Preserving memory ordering between offloaded instructions and non-offloaded inst2025
Preserving memory ordering between offloaded instructions and non-offloaded inst2025
Prismatic battery can with a thermally conductive insert2025
Modifying system directory capacity based on power state transition2025
Semiconductor device for performing data reduction for processing arrays2025
Super-temporal cache replacement policy2025
Super-temporal cache replacement policy2025
Systems and methods for branch misprediction aware cache prefetcher training2025
Systems and methods for branch misprediction aware cache prefetcher training2025
Smart cache cleaner2025