Issued Patents All Time
Showing 25 most recent of 65 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12394683 | Molded semiconductor chip package with stair-step molding layer | Priyal Shah, Rahul Agarwal, Chia-Hao Cheng | 2025-08-19 |
| 12266585 | Arrangement and thermal management of 3D stacked dies | John Wuu, Samuel D. Naffziger, Patrick J. Shyvers, Kaushik Mysore, Brett P. Wilkerson | 2025-04-01 |
| 12249519 | Molded chip package with anchor structures | Priyal Shah, Brett P. Wilkerson, Lei Fu, Rahul Agarwal | 2025-03-11 |
| 12183675 | Fan-out packages with warpage resistance | Rahul Agarwal, Chia-Hao Cheng | 2024-12-31 |
| 12170263 | Fabricating active-bridge-coupled GPU chiplets | Skyler Jonathon Saleh, Ruijin Wu, Rahul Agarwal | 2024-12-17 |
| 11855061 | Offset-aligned three-dimensional integrated circuit | Brett P. Wilkerson, Rahul Agarwal, Dmitri Yudanov | 2023-12-26 |
| 11841803 | GPU chiplets using high bandwidth crosslinks | Skyler Jonathon Saleh, Samuel D. Naffziger, Rahul Agarwal | 2023-12-12 |
| 11837588 | Circuit board with compact passive component arrangement | Rahul Agarwal | 2023-12-05 |
| 11810891 | Bond pads for low temperature hybrid bonding | Priyal Shah | 2023-11-07 |
| 11804479 | Scheme for enabling die reuse in 3D stacked products | John Wuu, Brett P. Wilkerson, Rahul Agarwal | 2023-10-31 |
| 11742301 | Fan-out package with reinforcing rivets | Rahul Agarwal, Priyal Shah, Chia-Hao Cheng, Brett P. Wilkerson, Lei Fu | 2023-08-29 |
| 11715691 | Integrated circuit package with integrated voltage regulator | Rahul Agarwal, Chia-Hao Cheng | 2023-08-01 |
| 11676924 | Semiconductor chip with reduced pitch conductive pillars | Priyal Shah, Lei Fu | 2023-06-13 |
| 11670624 | Integrated circuit module with integrated discrete devices | Rahul Agarwal | 2023-06-06 |
| 11658123 | Hybrid bridged fanout chiplet connectivity | Rahul Agarwal | 2023-05-23 |
| 11495588 | Circuit board with compact passive component arrangement | Rahul Agarwal | 2022-11-08 |
| 11469183 | Multirow semiconductor chip connections | Rahul Agarwal | 2022-10-11 |
| 11437359 | Offset-aligned three-dimensional integrated circuit | Brett P. Wilkerson, Rahul Agarwal, Dmitri Yudanov | 2022-09-06 |
| 11393697 | Semiconductor chip gettering | Rahul Agarwal, Ivor G. Barber, Venkatachalam Valliappan, Yuen Ting Cheng, Guan Sin Chok | 2022-07-19 |
| 11367628 | Molded chip package with anchor structures | Priyal Shah, Brett P. Wilkerson, Lei Fu, Rahul Agarwal | 2022-06-21 |
| 11309222 | Semiconductor chip with solder cap probe test pads | Lei Fu, Chia-Hao Cheng | 2022-04-19 |
| 11211332 | Molded die last chip combination | Rahul Agarwal | 2021-12-28 |
| 11189540 | Arrangement and thermal management of 3D stacked dies | John Wuu, Samuel D. Naffziger, Patrick J. Shyvers, Kaushik Mysore, Brett P. Wilkerson | 2021-11-30 |
| 11164807 | Arrangement and thermal management of 3D stacked dies | John Wuu, Samuel D. Naffziger, Patrick J. Shyvers, Kaushik Mysore, Brett P. Wilkerson | 2021-11-02 |
| 11018125 | Multi-chip package with offset 3D structure | Rahul Agarwal, Gabriel H. Loh | 2021-05-25 |