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USPTO Patent Rankings Data through Dec 31, 2025
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Ruijin Wu — 29 Patents

AMD: 34 patents #275 of 9,280Top 3%
Qualcomm: 1 patents #7,593 of 12,104Top 65%
Irvine, CA: #303 of 6,241 inventorsTop 5%
California: #18,137 of 386,348 inventorsTop 5%
Overall (All Time): #127,851 of 4,157,543Top 4%
29 Patents All Time
Ruijin Wu has been granted 29 US patents while listed as an inventor at AMD. The first was granted in 2018 and the most recent in August 2025. Ruijin Wu ranks #127,851 of 4,157,543 US inventors in our database (top 3.1%). Patent records list Ruijin Wu in Irvine, CA, US.

Issued Patents All Time

Showing 1–25 of 29 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12394010 Pipeline delay elimination with parallel two level primitive batch binning Michael John Livesley 2025-08-19
12266030 Processing system with selective priority-based two-level binning Anirudh R. Acharya, Young In Yeo 2025-04-01
12205193 Device and method of implementing subpass interleaving of tiled image rendering Michael John Livesley, Kiia Kallio, Jan H. Achrenius, Mika Tuomi 2025-01-21
12170263 Fabricating active-bridge-coupled GPU chiplets Skyler Jonathon Saleh, Milind S. Bhagavat, Rahul Agarwal 2024-12-17 $286,725,000
12154224 Fine grained replay control in binning hardware Jan H. Achrenius, Kiia Kallio, Miikka Kangasluoma, Anirudh R. Acharya 2024-11-26 $172,029,000
12118656 VRS rate feedback Skyler Jonathon Saleh, Vineet Goel, Pazhani Pillai, Christopher J. Brennan, Andrew S. Pomianowski 2024-10-15 $230,783,000
12086899 Graphics processing unit with selective two-level binning Anirudh R. Acharya, Paul E. Ruggieri 2024-09-10 $408,541,000
12051154 Systems and methods for distributed rendering using two-level binning Anirudh R. Acharya 2024-07-30 $352,866,000
12014527 Delta triplet index compression Kiia Kallio, Mika Tuomi, Anirudh R. Acharya 2024-06-18 $358,115,000
11972518 Hybrid binning Mika Tuomi, Kiia Kallio, Anirudh R. Acharya, Vineet Goel 2024-04-30 $818,790,000
11900499 Iterative indirect command buffers Anirudh R. Acharya, Alexander Fuad Ashkar, Harry J. Wise 2024-02-13 $405,375,000
11880924 Synchronization free cross pass binning through subpass interleaving Mika Tuomi, Paavo Sampo Ilmari Pessi, Anirudh R. Acharya 2024-01-23 $234,019,000
11748935 Bounding volume hierarchy traversal Skyler Jonathon Saleh 2023-09-05 $300,372,000
11741653 Overlapping visibility and render passes for same frame Mika Tuomi, Anirudh R. Acharya, Kiia Kallio 2023-08-29 $158,005,000
11715253 Pixelation optimized delta color compression Skyler Jonathon Saleh, Christopher J. Brennan, Kei Ming Kwong, Anthony Chan 2023-08-01 $238,969,000
11694367 Compressing texture data on a per-channel basis Saurabh Sharma, Laurent Lefebvre, Sagar S. Bhandare 2023-07-04
11657560 VRS rate feedback Skyler Jonathon Saleh, Vineet Goel, Pazhani Pillai, Christopher J. Brennan, Andrew S. Pomianowski 2023-05-23 $168,136,000
11507527 Active bridge chiplet with integrated cache Skyler Jonathon Saleh 2022-11-22 $130,453,000
11308648 Compressing texture data on a per-channel basis Saurabh Sharma, Laurent Lefebvre, Sagar S. Bhandare 2022-04-19 $202,720,000
11232622 Data flow in a distributed graphics processing unit architecture Skyler Jonathon Saleh 2022-01-25 $180,690,000
11195326 Method and system for depth pre-processing and geometry sorting using binning hardware Young In Yeo, Sagar S. Bhandare, Vineet Goel, Martin G. Sarov, Christopher J. Brennan 2021-12-07 $228,692,000
11158106 VRS rate feedback Skyler Jonathon Saleh, Vineet Goel, Pazhani Pillai, Christopher J. Brennan, Andrew S. Pomianowski 2021-10-26 $390,244,000
11037357 Pixelation optimized delta color compression Skyler Jonathon Saleh, Christopher J. Brennan, Kei Ming Kwong, Anthony Chan 2021-06-15 $262,158,000
10783694 Texture residency checks using compression metadata Maxim V. Kazakov, Skyler Jonathon Saleh, Sagar S. Bhandare 2020-09-22 $76,515,000
10706609 Efficient data path for ray triangle intersection Skyler Jonathon Saleh 2020-07-07 $35,622,000