Issued Patents All Time
Showing 25 most recent of 29 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12394010 | Pipeline delay elimination with parallel two level primitive batch binning | Michael John Livesley | 2025-08-19 |
| 12266030 | Processing system with selective priority-based two-level binning | Anirudh R. Acharya, Young In Yeo | 2025-04-01 |
| 12205193 | Device and method of implementing subpass interleaving of tiled image rendering | Michael John Livesley, Kiia Kallio, Jan H. Achrenius, Mika Tuomi | 2025-01-21 |
| 12170263 | Fabricating active-bridge-coupled GPU chiplets | Skyler Jonathon Saleh, Milind S. Bhagavat, Rahul Agarwal | 2024-12-17 |
| 12154224 | Fine grained replay control in binning hardware | Jan H. Achrenius, Kiia Kallio, Miikka Kangasluoma, Anirudh R. Acharya | 2024-11-26 |
| 12118656 | VRS rate feedback | Skyler Jonathon Saleh, Vineet Goel, Pazhani Pillai, Christopher J. Brennan, Andrew S. Pomianowski | 2024-10-15 |
| 12086899 | Graphics processing unit with selective two-level binning | Anirudh R. Acharya, Paul E. Ruggieri | 2024-09-10 |
| 12051154 | Systems and methods for distributed rendering using two-level binning | Anirudh R. Acharya | 2024-07-30 |
| 12014527 | Delta triplet index compression | Kiia Kallio, Mika Tuomi, Anirudh R. Acharya | 2024-06-18 |
| 11972518 | Hybrid binning | Mika Tuomi, Kiia Kallio, Anirudh R. Acharya, Vineet Goel | 2024-04-30 |
| 11900499 | Iterative indirect command buffers | Anirudh R. Acharya, Alexander Fuad Ashkar, Harry J. Wise | 2024-02-13 |
| 11880924 | Synchronization free cross pass binning through subpass interleaving | Mika Tuomi, Paavo Sampo Ilmari Pessi, Anirudh R. Acharya | 2024-01-23 |
| 11748935 | Bounding volume hierarchy traversal | Skyler Jonathon Saleh | 2023-09-05 |
| 11741653 | Overlapping visibility and render passes for same frame | Mika Tuomi, Anirudh R. Acharya, Kiia Kallio | 2023-08-29 |
| 11715253 | Pixelation optimized delta color compression | Skyler Jonathon Saleh, Christopher J. Brennan, Kei Ming Kwong, Anthony Chan | 2023-08-01 |
| 11694367 | Compressing texture data on a per-channel basis | Saurabh Sharma, Laurent Lefebvre, Sagar S. Bhandare | 2023-07-04 |
| 11657560 | VRS rate feedback | Skyler Jonathon Saleh, Vineet Goel, Pazhani Pillai, Christopher J. Brennan, Andrew S. Pomianowski | 2023-05-23 |
| 11507527 | Active bridge chiplet with integrated cache | Skyler Jonathon Saleh | 2022-11-22 |
| 11308648 | Compressing texture data on a per-channel basis | Saurabh Sharma, Laurent Lefebvre, Sagar S. Bhandare | 2022-04-19 |
| 11232622 | Data flow in a distributed graphics processing unit architecture | Skyler Jonathon Saleh | 2022-01-25 |
| 11195326 | Method and system for depth pre-processing and geometry sorting using binning hardware | Young In Yeo, Sagar S. Bhandare, Vineet Goel, Martin G. Sarov, Christopher J. Brennan | 2021-12-07 |
| 11158106 | VRS rate feedback | Skyler Jonathon Saleh, Vineet Goel, Pazhani Pillai, Christopher J. Brennan, Andrew S. Pomianowski | 2021-10-26 |
| 11037357 | Pixelation optimized delta color compression | Skyler Jonathon Saleh, Christopher J. Brennan, Kei Ming Kwong, Anthony Chan | 2021-06-15 |
| 10783694 | Texture residency checks using compression metadata | Maxim V. Kazakov, Skyler Jonathon Saleh, Sagar S. Bhandare | 2020-09-22 |
| 10706609 | Efficient data path for ray triangle intersection | Skyler Jonathon Saleh | 2020-07-07 |