| 12309035 |
Analyses and topology visualizations of network devices and networks |
Abilash Menon, Payal Vrajlal Gothi |
2025-05-20 |
| 7827355 |
Data processor having a cache with efficient storage of predecode information, cache, and method |
Brian D. McMinn |
2010-11-02 |
| 7366885 |
Method for optimizing loop control of microcoded instructions |
Arun Radhakrishnan |
2008-04-29 |
| 6738792 |
Parallel mask generator |
— |
2004-05-18 |
| 6253316 |
Three state branch history using one bit in a branch prediction mechanism |
Thang M. Tran, Andrew McBride |
2001-06-26 |
| 6108774 |
Branch prediction with added selector bits to increase branch prediction capacity and flexibility with minimal added bits |
— |
2000-08-22 |
| 6076146 |
Cache holding register for delayed update of a cache line into an instruction cache |
Thang M. Tran, Rammohan Narayan, Andrew McBride |
2000-06-13 |
| 6049863 |
Predecoding technique for indicating locations of opcode bytes in variable byte-length instructions within a superscalar microprocessor |
Thang M. Tran, Rammohan Narayan, Andrew McBride |
2000-04-11 |
| 5983321 |
Cache holding register for receiving instruction packets and for providing the instruction packets to a predecode unit and instruction cache |
Thang M. Tran, Rammohan Narayan, Andrew McBride |
1999-11-09 |
| 5961581 |
Method and circuit for detecting address limit violations in a microprocessor-based computer |
— |
1999-10-05 |
| 5954816 |
Branch selector prediction |
Thang M. Tran, David E. Kroesche, Andrew McBride |
1999-09-21 |
| 5900013 |
Dual comparator scheme for detecting a wrap-around condition and generating a cancel signal for removing wrap-around buffer entries |
Rammohan Narayan |
1999-05-04 |
| 5862065 |
Method and circuit for fast generation of zero flag condition code in a microprocessor-based computer |
— |
1999-01-19 |
