Issued Patents All Time
Showing 26–37 of 37 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5727177 | Reorder buffer circuit accommodating special instructions operating on odd-width results | Robert Douglas Gowin, Jr. | 1998-03-10 |
| 5721695 | Simulation by emulating level sensitive latches with edge trigger latches | Gopi Ganapathy | 1998-02-24 |
| 5646893 | Segmented read line circuit particularly useful for multi-port storage arrays | R. Tod Calvin | 1997-07-08 |
| 5570294 | Circuit configuration employing a compare unit for testing variably controlled delay units | Stephen C. Horne | 1996-10-29 |
| 5430394 | Configuration and method for testing a delay chain within a microprocessor clock generator | Stephen C. Horne | 1995-07-04 |
| 5327571 | Processor having decoder for decoding unmodified instruction set for addressing register to read or write in parallel or serially shift in from left or right | Robert H. Perlman, Prem Sobel | 1994-07-05 |
| 5267186 | Normalizing pipelined floating point processing unit | Smeeta Gupta, Robert M. Perlman, Thomas W. Lynch | 1993-11-30 |
| 5077692 | Information storage device with batch select capability | — | 1991-12-31 |
| 5059818 | Self-regulating clock generator | David B. Witt | 1991-10-22 |
| 5058048 | Normalizing pipelined floating point processing unit | Smeeta Gupta, Robert M. Perlman, Thomas W. Lynch | 1991-10-15 |
| 5053631 | Pipelined floating point processing unit | Robert M. Perlman, Prem Sobel, Robert C. Thaden, Glenn A. Tamura, Thomas W. Lynch +1 more | 1991-10-01 |
| 4731737 | High speed intelligent distributed control memory system | David B. Witt | 1988-03-15 |