Issued Patents All Time
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12282439 | Dynamic page state aware scheduling of read/write burst transactions | Ravindra N. Bhargava, Kedarnath Balakrishnan | 2025-04-22 |
| 12253961 | Staging memory access requests | James R. Magro, Kedarnath Balakrishnan, Ravindra N. Bhargava | 2025-03-18 |
| 12118247 | Performance of bank refresh | Kedarnath Balakrishnan, Jing Wang | 2024-10-15 |
| 11995008 | Memory controller with hybrid DRAM/persistent memory channel arbitration | Ravindra N. Bhargava, James R. Magro, Kedarnath Balakrishnan | 2024-05-28 |
| 11789655 | Efficient and low latency memory access scheduling | Ravindra N. Bhargava | 2023-10-17 |
| 11782640 | Efficient and low latency memory access scheduling | Ravindra N. Bhargava | 2023-10-10 |
| 11755246 | Efficient rank switching in multi-rank memory controller | Ravindra N. Bhargava | 2023-09-12 |
| 11694739 | Refresh management for memory | Kevin M. Brandl, Kedarnath Balakrishnan, Jing Wang | 2023-07-04 |
| 11687281 | DRAM command streak efficiency management | Ravindra N. Bhargava | 2023-06-27 |
| 11625352 | DRAM command streak management | Ravindra N. Bhargava, Raghava Sravan Adidamu | 2023-04-11 |
| 11526278 | Adaptive page close prediction | Ravindra N. Bhargava, James R. Magro, Kedarnath Balakrishnan, Kevin M. Brandl | 2022-12-13 |
| 11222685 | Refresh management for DRAM | Kevin M. Brandl, Kedarnath Balakrishnan, Jing Wang | 2022-01-11 |
| 10846253 | Dynamic page state aware scheduling of read/write burst transactions | Ravindra N. Bhargava, Kedarnath Balakrishnan | 2020-11-24 |
| 10503670 | Dynamic per-bank and all-bank refresh | Ravindra N. Bhargava, James R. Magro, Kedarnath Balakrishnan, Jing Wang | 2019-12-10 |
| 10403333 | Memory controller with flexible address decoding | Kevin M. Brandl, Thomas H. Hamilton, Hideki Kanayama, Kedarnath Balakrishnan, James R. Magro +1 more | 2019-09-03 |