Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12174769 | Periodic receiver clock data recovery with dynamic data edge | Gurunath Dollin, Edoardo Prete, Milam Paraschou, Edward Wade Thoenes, Gerald R. Talbot | 2024-12-24 |
| 11169810 | Micro-operation cache using predictive allocation | Fuzhou Zou, Monika TKACZYK, Eric C. Quinnell, James David Dundas, Madhu Saravana Sibi Govindan | 2021-11-09 |
| 10891135 | Register renaming of a shareable instruction operand cache | Paul Kitchin, Nicholas T. Humphries, Ken Yu Lim | 2021-01-12 |
| 8607104 | Memory diagnostics system and method with hardware-based read/write patterns | Hanwoo Cho, Tahsin Askar, Philip E. Madrid, Guhan Krishnan, Brian Amick +1 more | 2013-12-10 |
| 8373447 | Method and apparatus of alternating service modes of an SOI process circuit | Joseph Kidd, Brian Amick, James R. Magro, Ronald L. Pettyjohn | 2013-02-12 |
| 8358158 | Method and apparatus for phase selection acceleration | Brian Amick, Warren Anderson, Joseph Kidd | 2013-01-22 |
| 7139859 | Inter-queue ordering mechanism | Jaideep Dastidar, Michael Ruhovets, An H. Lam | 2006-11-21 |
| 7111105 | System to optimally order cycles originating from a single physical link | Paras A. Shah, Jaideep Dastidar | 2006-09-19 |
| 7000060 | Method and apparatus for ordering interconnect transactions in a computer system | Paras A. Shah | 2006-02-14 |
| 6950897 | Method and apparatus for a dual mode PCI/PCI-X device | Jaideep Dastidar, Timothy K. Waldrop | 2005-09-27 |
| 6941407 | Method and apparatus for ordering interconnect transactions in a computer system | Paras A. Shah, Randall Pascarella | 2005-09-06 |