Issued Patents All Time
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12367157 | Compressing translation lookaside buffer (TLB) tags using a TLB metadata buffer in processor-based devices | Adrian Montero, Conrado Blasco, Huzefa Sanjeliwala | 2025-07-22 |
| 12135652 | Filtering remote data synchronization barrier (DSB) instruction execution in processor-based devices | Adrian Montero, Huzefa Sanjeliwala | 2024-11-05 |
| 12130751 | Compressing translation lookaside buffer (TLB) tags using a TLB metadata buffer in processor-based devices | Adrian Montero, Conrado Blasco, Huzefa Sanjeliwala | 2024-10-29 |
| 11914524 | Latency management in synchronization events | Adrian Montero, Huzefa Sanjeliwala, Prarthna Santhanakrishnan, Conrado Blasco, Pradeep Kanapathipillai | 2024-02-27 |
| 10956155 | Memory load to load fusing | Rama S. Gopal, Karthik Sundaram | 2021-03-23 |
| 10891135 | Register renaming of a shareable instruction operand cache | Nicholas T. Humphries, Ken Yu Lim, Ryan J. Hensley | 2021-01-12 |
| 10649900 | Method to avoid cache access conflict between load and fill | Tarun Nakra, Hao Wang | 2020-05-12 |
| 10372452 | Memory load to load fusing | Rama S. Gopal, Karthik Sundaram | 2019-08-06 |
| 10296463 | Instruction prefetcher dynamically controlled by readily available prefetcher accuracy | — | 2019-05-21 |
| 10275217 | Memory load and arithmetic load unit (ALU) fusing | Rama S. Gopal, Karthik Sundaram | 2019-04-30 |
| 9383801 | Methods and apparatus related to processor sleep states | Alexander J. Branover, Andrew W. Lueck, David A. Kaplan | 2016-07-05 |
| 9317100 | Accelerated cache rinse when preparing a power state transition | William L. Walker | 2016-04-19 |
| 9286073 | Read-after-write hazard predictor employing confidence and sampling | Gerald D. Zuraski, Jr., Brian C. Grayson | 2016-03-15 |
| 9274970 | Method and apparatus for handling processor read-after-write hazards with cache misses | — | 2016-03-01 |
| 9182999 | Reintialization of a processing system from volatile memory upon resuming from a low-power state | Andrew W. Lueck, Krishna Sai Bernucho, Alexander J. Branover, Ronald Perez, Sonu Arora | 2015-11-10 |
| 9043628 | Power management of multiple compute units sharing a cache | William L. Walker, Steven J. Kommrusch | 2015-05-26 |