Issued Patents All Time
Showing 26–50 of 61 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8553754 | Method and apparatus for using DFE in a system with non-continuous data | Ramon Mangaser, Shefali Walia, Edoardo Prete, Jonathan P. Dowling, Sharad N. Vittal | 2013-10-08 |
| 8274272 | Programmable delay module testing device and methods thereof | Hanwoo Cho, Brian Amick | 2012-09-25 |
| 8019907 | Memory controller including a dual-mode memory interconnect | — | 2011-09-13 |
| 8000404 | Method and apparatus to reduce the effect of crosstalk in a communications interface | Paul C. Miranda | 2011-08-16 |
| 7986727 | In-band method to configure equalization levels | Larry D. Hewitt, Paul C. Miranda, Rohit Kumar, Emerson S. Fang | 2011-07-26 |
| 7929549 | Method and apparatus for scrambling data for control of high-speed bidirectional signaling | — | 2011-04-19 |
| 7861140 | Memory system including asymmetric high-speed differential memory interconnect | — | 2010-12-28 |
| 7783954 | System for controlling high-speed bidirectional communication | — | 2010-08-24 |
| 7729465 | Asymmetric control of high-speed bidirectional signaling | R. Stephen Polzin | 2010-06-01 |
| 7721160 | System for protecting data during high-speed bidirectional communication between a master device and a slave device | — | 2010-05-18 |
| 7694031 | Memory controller including a dual-mode memory interconnect | — | 2010-04-06 |
| 7613266 | Binary controlled phase selector with output duty cycle correction | — | 2009-11-03 |
| 7613237 | Built-in test feature to facilitate system level stress testing of a high-speed serial link that uses a forwarding clock | — | 2009-11-03 |
| 7561625 | Method and apparatus for crosstalk reduction | Shawn Searles | 2009-07-14 |
| 7506222 | System for phase tracking and equalization across a byte group for asymmetric control of high-speed bidirectional signaling | — | 2009-03-17 |
| 7505332 | Input offset correction for asymmetric control of high-speed bidirectional signaling | — | 2009-03-17 |
| 7421525 | System including a host connected to a plurality of memory modules via a serial memory interconnect | R. Stephen Polzin, Frederick Daniel Weber, Larry D. Hewitt, Richard W. Reeves, Shwetal Arvind Patel +4 more | 2008-09-02 |
| 7358771 | System including a single ended switching topology for high-speed bidirectional signaling | — | 2008-04-15 |
| 7308620 | Method to obtain the worst case transmit data and jitter pattern that minimizes the receiver's data eye for arbitrary channel model | — | 2007-12-11 |
| 7269681 | Arrangement for receiving and transmitting PCI-X data according to selected data modes | Austen J. Hypher, Richard W. Reeves | 2007-09-11 |
| 7256627 | Alignment of local transmit clock to synchronous data transfer clock having programmable transfer rate | Richard W. Reeves | 2007-08-14 |
| 7248125 | Poly-phase VCO with rail to rail output voltage swing and duty cycle control across tuning range | — | 2007-07-24 |
| 7227382 | Transmit based equalization using a voltage mode driver | Rohit Kumar, Stephen C. Hale | 2007-06-05 |
| 7221192 | Voltage access circuit configured for outputting a selected analog voltage signal for testing external to an integrated circuit | — | 2007-05-22 |
| 7154309 | Dual-mode output driver configured for outputting a signal according to either a selected high voltage/low speed mode or a low voltage/high speed mode | Randall Paul Biesterfeldt | 2006-12-26 |