SP

Shwetal Arvind Patel

IT Integrated Device Technology: 7 patents #83 of 758Top 15%
AM AMD: 3 patents #3,141 of 9,279Top 35%
Globalfoundries: 1 patents #2,221 of 4,424Top 55%
RA Renesas Electronics America: 1 patents #121 of 293Top 45%
Overall (All Time): #408,398 of 4,157,543Top 10%
12
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
11815978 DDR5 client PMIC power up sequence and state transitions Chenxiao Ren 2023-11-14
11249539 DDR5 client PMIC power up sequence and state transitions Chenxiao Ren 2022-02-15
10776293 DDR5 RCD interface protocol and operation Andy Zhang, Wen Jie Meng, Chenxiao Ren, Alejandro F. Gonzalez 2020-09-15
10769082 DDR5 PMIC interface protocol and operation Andy Zhang, Wen Jie Meng, Chenxiao Ren, Alejandro F. Gonzalez 2020-09-08
10401899 Register clock driver for DDR5 memory 2019-09-03
10394460 Enhanced data buffer and intelligent NV controller for simultaneous DRAM and flash memory access 2019-08-27
9847112 Synchronization of data transmission with a clock signal after a memory mode switch 2017-12-19
9552870 Memory includes transmitter for data synchronization transmission after a mode switch and method thereof 2017-01-24
8260992 Reducing simultaneous switching outputs using data bus inversion signaling Glenn Dearth 2012-09-04
8019921 Intelligent memory buffer 2011-09-13
7421525 System including a host connected to a plurality of memory modules via a serial memory interconnect R. Stephen Polzin, Frederick Daniel Weber, Gerald R. Talbot, Larry D. Hewitt, Richard W. Reeves +4 more 2008-09-02
6957308 DRAM supporting different burst-length accesses without changing the burst length setting in the mode register 2005-10-18