Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10956349 | Support for multiple widths of DRAM in double data rate controllers or data buffers | Craig DeSimone, Garret Davey, Yue Yu, Roland T. Knaack, Scott Herrington | 2021-03-23 |
| 10776293 | DDR5 RCD interface protocol and operation | Shwetal Arvind Patel, Andy Zhang, Wen Jie Meng, Chenxiao Ren | 2020-09-15 |
| 10769082 | DDR5 PMIC interface protocol and operation | Shwetal Arvind Patel, Andy Zhang, Wen Jie Meng, Chenxiao Ren | 2020-09-08 |
| 10671300 | Command sequence response in a memory data buffer | Craig DeSimone, Praveen R. Singh, Yue Yu, Yanbo Wang | 2020-06-02 |
| 10565144 | Double data rate controllers and data buffers with support for multiple data widths of DRAM | Craig DeSimone, Garret Davey, Yue Yu, Roland T. Knaack, Scott Herrington | 2020-02-18 |
| 10325637 | Flexible point-to-point memory topology | — | 2019-06-18 |
| 10198200 | Command sequence response in a memory data buffer | Craig DeSimone, Praveen R. Singh, Yue Yu, Yanbo Wang | 2019-02-05 |
| 10032497 | Flexible point-to-point memory topology | — | 2018-07-24 |
| 9860088 | Inferring sampled data in decision feedback equalizer at restart of forwarded clock in memory system | Craig DeSimone, Praveen R. Singh, Yue Yu, Yanbo Wang | 2018-01-02 |
| 8693557 | AC coupled clock receiver with common-mode noise rejection | Liang Zhang | 2014-04-08 |
| 8513992 | Method and apparatus for implementation of PLL minimum frequency via voltage comparison | Amit Majumder, Praveen R. Singh | 2013-08-20 |
| 7555668 | DRAM interface circuits that support fast deskew calibration and methods of operating same | Paul Murtagh, Prashant Shamarao | 2009-06-30 |