Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
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Alejandro F. Gonzalez — 12 Patents

ITIntegrated Device Technology: 12 patents #33 of 758Top 5%
Johns Creek, GA: #57 of 271 inventorsTop 25%
Georgia: #2,791 of 35,610 inventorsTop 8%
Overall (All Time): #396,045 of 4,157,543Top 10%
12 Patents All Time
Alejandro F. Gonzalez has been granted 12 US patents while listed as an inventor at Integrated Device Technology. The first was granted in 2009 and the most recent in March 2021. Alejandro F. Gonzalez ranks #396,045 of 4,157,543 US inventors in our database (top 9.5%). Patent records list Alejandro F. Gonzalez in Johns Creek, GA, US.

Issued Patents All Time

Showing 1–12 of 12 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
10956349 Support for multiple widths of DRAM in double data rate controllers or data buffers Craig DeSimone, Garret Davey, Yue Yu, Roland T. Knaack, Scott Herrington 2021-03-23
10776293 DDR5 RCD interface protocol and operation Shwetal Arvind Patel, Andy Zhang, Wen Jie Meng, Chenxiao Ren 2020-09-15
10769082 DDR5 PMIC interface protocol and operation Shwetal Arvind Patel, Andy Zhang, Wen Jie Meng, Chenxiao Ren 2020-09-08
10671300 Command sequence response in a memory data buffer Craig DeSimone, Praveen R. Singh, Yue Yu, Yanbo Wang 2020-06-02
10565144 Double data rate controllers and data buffers with support for multiple data widths of DRAM Craig DeSimone, Garret Davey, Yue Yu, Roland T. Knaack, Scott Herrington 2020-02-18
10325637 Flexible point-to-point memory topology 2019-06-18
10198200 Command sequence response in a memory data buffer Craig DeSimone, Praveen R. Singh, Yue Yu, Yanbo Wang 2019-02-05 $10,227,000
10032497 Flexible point-to-point memory topology 2018-07-24 $29,070,000
9860088 Inferring sampled data in decision feedback equalizer at restart of forwarded clock in memory system Craig DeSimone, Praveen R. Singh, Yue Yu, Yanbo Wang 2018-01-02 $6,945,000
8693557 AC coupled clock receiver with common-mode noise rejection Liang Zhang 2014-04-08 $13,077,000
8513992 Method and apparatus for implementation of PLL minimum frequency via voltage comparison Amit Majumder, Praveen R. Singh 2013-08-20 $2,770,000
7555668 DRAM interface circuits that support fast deskew calibration and methods of operating same Paul Murtagh, Prashant Shamarao 2009-06-30 $5,559,000