Issued Patents All Time
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10956349 | Support for multiple widths of DRAM in double data rate controllers or data buffers | Alejandro F. Gonzalez, Craig DeSimone, Garret Davey, Yue Yu, Roland T. Knaack | 2021-03-23 |
| 10565144 | Double data rate controllers and data buffers with support for multiple data widths of DRAM | Alejandro F. Gonzalez, Craig DeSimone, Garret Davey, Yue Yu, Roland T. Knaack | 2020-02-18 |
| 9667064 | Daisy chain configuration for power converters | James W. Templeton, Gregg S. Kodra, Paul W. Latham, II, Stewart Kenly | 2017-05-30 |
| 9164560 | Daisy chain configuration for power converters | James W. Templeton, Gregg S. Kodra, Paul W. Latham, II, Stewart Kenly | 2015-10-20 |
| 7502468 | Method and system for generating a cryptographically random number stream | George Robert Blakley, III, Randall Findley, Richard Goble, Kyle Stein | 2009-03-10 |
| 7239257 | Hardware efficient digital control loop architecture for a power converter | Mark A. Alexander, Douglas E. Heineman, Kenneth W. Fernald | 2007-07-03 |
| 6425115 | Area efficient delay circuits | Daniel A. Risler | 2002-07-23 |
| 5357156 | Active clamp circuit scheme for CMOS devices | — | 1994-10-18 |