DR

Daniel A. Risler

ET Ess Tech: 3 patents #26 of 112Top 25%
Overall (All Time): #1,507,710 of 4,157,543Top 40%
3
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
9361419 Constrained placement of connected elements Robert Lynn Blair, A Martin Mallinson 2016-06-07
6425115 Area efficient delay circuits Scott Herrington 2002-07-23
6223330 System and method for designing integrated circuits using cells with multiple unrelated outputs 2001-04-24