Issued Patents All Time
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10956349 | Support for multiple widths of DRAM in double data rate controllers or data buffers | Alejandro F. Gonzalez, Garret Davey, Yue Yu, Roland T. Knaack, Scott Herrington | 2021-03-23 |
| 10671300 | Command sequence response in a memory data buffer | Praveen R. Singh, Alejandro F. Gonzalez, Yue Yu, Yanbo Wang | 2020-06-02 |
| 10565144 | Double data rate controllers and data buffers with support for multiple data widths of DRAM | Alejandro F. Gonzalez, Garret Davey, Yue Yu, Roland T. Knaack, Scott Herrington | 2020-02-18 |
| 10311940 | Nullifying incorrect sampled data contribution in decision feedback equalizer at restart of forwarded clock in memory system | Praveen R. Singh | 2019-06-04 |
| 10311926 | Compensation of deterministic crosstalk in memory system | — | 2019-06-04 |
| 10198200 | Command sequence response in a memory data buffer | Praveen R. Singh, Alejandro F. Gonzalez, Yue Yu, Yanbo Wang | 2019-02-05 |
| 10171268 | Asymmetric on-state resistance driver optimized for multi-drop DDR4 | Yue Yu, Al Xuefeng Fang, Yanbo Wang | 2019-01-01 |
| 9905287 | Asymmetrical emphasis in a memory data bus driver | Yanbo Wang, Praveen R. Singh, Yue Yu | 2018-02-27 |
| 9865328 | Nullifying incorrect sampled data contribution in decision feedback equalizer at restart of forwarded clock in memory system | Praveen R. Singh | 2018-01-09 |
| 9865315 | Compensation of deterministic crosstalk in memory system | — | 2018-01-09 |
| 9860088 | Inferring sampled data in decision feedback equalizer at restart of forwarded clock in memory system | Praveen R. Singh, Alejandro F. Gonzalez, Yue Yu, Yanbo Wang | 2018-01-02 |
| 9794087 | Asymmetric on-state resistance driver optimized for multi-drop DDR4 | Yue Yu, Al Xuefeng Fang, Yanbo Wang | 2017-10-17 |
| 9653147 | Asymmetrical emphasis in a memory data bus driver | Yanbo Wang, Praveen R. Singh, Yue Yu | 2017-05-16 |