| 12417792 |
Jitter reduction in mixed-signal processing circuits |
Srikanth Reddy Gruddanti, David Lin, Manoj N. Kulkarni, Priyadarshi Saxena |
2025-09-16 |
| 12386750 |
Last level cache hierarchy in chiplet based processors |
Srikanth Reddy Gruddanti, Krishnaiah Gummidipudi, David Hugh McIntyre, Ramon Mangaser |
2025-08-12 |
| 12321294 |
Data lane variation compensation for data rate enhancement |
Srikanth Reddy Gruddanti, David Hugh McIntyre, Ramon Mangaser, Manoj N. Kulkarni |
2025-06-03 |
| 12231120 |
Apparatus, system, and method for improving latency or power consumption |
Jagadeesh Anathahalli Singrigowda, Girish A S, Aniket Bharat Waghide |
2025-02-18 |
| 12088296 |
Clock gating using a cascaded clock gating control signal |
Ramon Mangaser, Srikanth Reddy Gruddanti, Krishna Reddy Mudimela Venkata, Oikwan Tsang |
2024-09-10 |
| 12015412 |
Dual phase clock distribution from a single source in a die-to-die interface |
Srikanth Reddy Gruddanti, Pradeep Jayaraman, Ramon Mangaser, Krishna Reddy Mudimela Venkata, David Hugh McIntyre |
2024-06-18 |
| 11960435 |
Skew matching in a die-to-die interface |
Pradeep Jayaraman, Dean E. Gonzales, Gerald R. Talbot, Ramon Mangaser, Michael J. Tresidder +3 more |
2024-04-16 |
| 11764789 |
Adaptive biasing circuit for serial communication interfaces |
Rajesh Mangalore Anand, Piyush Gupta, Girish Anathahalli Singrigowda, Jagadeesh Anathahalli Singrigowda |
2023-09-19 |
| 11569819 |
High-voltage tolerant inverter |
Dhruvin Devangbhai Shah, Jagadeesh Anathahalli Singrigowda, Girish Anathahalli Singrigowda |
2023-01-31 |
| 11418187 |
Low voltage power on reset circuit |
Ashish Sahu, Aniket Bharat Waghide, Girish Anathahalli Singrigowda |
2022-08-16 |
| 11418189 |
High voltage output circuit with low voltage devices using data dependent dynamic biasing |
Jagadeesh Anathahalli Singrigowda, Ashish Sahu, Rajesh Mangalore Anand, Aniket Bharat Waghide, Girish Anathahalli Singrigowda |
2022-08-16 |
| 10715139 |
Gate-source voltage generation for pull-up and pull-down devices in I/O designs |
Rajesh Mangalore Anand, Jagadeesh Anathahalli Singrigowda, Girish Anathahalli Singrigowda |
2020-07-14 |
| 9625938 |
Integrated differential clock gater |
Hariprasad Thodukattil Thazhatheppattu, Animesh Sharma |
2017-04-18 |
| 7205924 |
Circuit for high-resolution phase detection in a digital RF processor |
Sudheer K. Vemulapalli, John Wallberg, Robert Bogdan Staszewski |
2007-04-17 |