Issued Patents All Time
Showing 25 most recent of 34 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12423019 | Read gate training and tracking | Ronald L. Pettyjohn, Pouya Najafi Ashtiani, Gershom Birk, Anwar Kashem | 2025-09-23 |
| 12417792 | Jitter reduction in mixed-signal processing circuits | Srikanth Reddy Gruddanti, Prasant Kumar Vallur, Manoj N. Kulkarni, Priyadarshi Saxena | 2025-09-16 |
| 12348591 | Network computer system to selectively engage users based on friction analysis | Manish Malhotra, Huy Le, Azhar Zeeshan, Siddartha Sikdar, Tom Liu | 2025-07-01 |
| 12113686 | Predicting network anomaly events | Garima Juneja, Wanpeng Liu, Harsh Bhattachar, Bing Zhang | 2024-10-08 |
| 12061516 | Determining false positive and active event data | Garima Juneja, Wanpeng Liu, Harsh Bhattachar, Bing Zhang | 2024-08-13 |
| 11569806 | Duty cycle adjustment circuit with independent range and step size control | Kuan Zhou, Vladimir Zlatkovic, Shefali Walia, Youssef Mamdouh El-Toukhy, Abdelrahman Alaa Gouda +1 more | 2023-01-31 |
| 11456052 | Write and read common leveling for 4-bit wide drams | — | 2022-09-27 |
| 10892032 | Write and read common leveling for 4-bit wide DRAMS | — | 2021-01-12 |
| 10649025 | External DQS bi-directional loopback with use of feed forward equalization path | Edward Wade Thoenes | 2020-05-12 |
| 10635427 | Forward compatibility process | Yang Liu | 2020-04-28 |
| 10497413 | Write and read common leveling for 4-bit wide drams | — | 2019-12-03 |
| 10418125 | Write and read common leveling for 4-bit wide DRAMs | — | 2019-09-17 |
| 10050624 | Process-compensated level-up shifter circuit | — | 2018-08-14 |
| 9721627 | Method and apparatus for aligning signals | Thucydides Xanthopoulos, Edward Wade Thoenes | 2017-08-01 |
| 9613679 | Controlled dynamic de-alignment of clocks | Edward Wade Thoenes | 2017-04-04 |
| 9607672 | Managing skew in data signals with adjustable strobe | Edward Wade Thoenes | 2017-03-28 |
| 9601181 | Controlled multi-step de-alignment of clocks | Edward Wade Thoenes, Vasudevan Kandadi | 2017-03-21 |
| 9568542 | Memory interface with integrated tester | — | 2017-02-14 |
| 9570128 | Managing skew in data signals | Edward Wade Thoenes, Thucydides Xanthopoulos | 2017-02-14 |
| 9502099 | Managing skew in data signals with multiple modes | Edward Wade Thoenes | 2016-11-22 |
| 9496012 | Method and apparatus for reference voltage calibration in a single-ended receiver | Omer O. Yildirim, Scott E. Meninger | 2016-11-15 |
| 9413568 | Method and apparatus for calibrating an input interface | Omer O. Yildirim, Scott E. Meninger | 2016-08-09 |
| 9349434 | Variable strobe for alignment of partially invisible data signals | Edward Wade Thoenes | 2016-05-24 |
| 9306584 | Multi-function delay locked loop | Suresh Balasubramanian | 2016-04-05 |
| 9281034 | Data strobe generation | — | 2016-03-08 |