Issued Patents All Time
Showing 1–23 of 23 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12027229 | High speed differential rom | David J. Toops | 2024-07-02 |
| 11870442 | Hybrid pulse/two-stage data latch | Vivekanandan Venugopal, Raghava Rao V. Denduluri, Ajay Bhatia, Suparn Vats, Gopinath Venkatesh +1 more | 2024-01-09 |
| 11762413 | Clock duty cycle correction | Sunil Bhosekar, Bruce A. Doyle, Chad O. Lackey, Sharath R. Srinivasan, Erick Omar Torres +1 more | 2023-09-19 |
| 11418173 | Hybrid pulse/two-stage data latch | Vivekanandan Venugopal, Raghava Rao V. Denduluri, Ajay Bhatia, Suparn Vats, Gopinath Venkatesh +1 more | 2022-08-16 |
| 11170864 | Methods and apparatus to improve performance while reading a one-time-programmable memory | Stephen Wayne Spriggs, George B. Jamison | 2021-11-09 |
| 11145378 | Methods and apparatus to improve performance while reading a one-time programmable memory | Stephen Wayne Spriggs, George B. Jamison | 2021-10-12 |
| 10742201 | Hybrid pulse/master-slave data latch | Vivekanandan Venugopal, Raghava Rao V. Denduluri, Ajay Bhatia, Suparn Vats, Gopinath Venkatesh +1 more | 2020-08-11 |
| 9417655 | Frequency division clock alignment | Steve Aiken, Georgios Faldamis | 2016-08-16 |
| 9411361 | Frequency division clock alignment using pattern selection | Steve Aiken, Georgios Faldamis | 2016-08-09 |
| 9335784 | Clock distribution circuit with distributed delay locked loop | — | 2016-05-10 |
| 9306584 | Multi-function delay locked loop | David Lin | 2016-04-05 |
| 9264023 | Scannable flop with a single storage element | — | 2016-02-16 |
| 9143140 | Multi-function delay locked loop | David Lin | 2015-09-22 |
| 9130549 | Multiplexer flop | Nitin Mohan, Manan Salvi | 2015-09-08 |
| 8963601 | Clock gated delay line based on setting value | — | 2015-02-24 |
| 8513994 | State machine for deskew delay locked loop | — | 2013-08-20 |
| 8381075 | Low-power redundancy for non-volatile memory | David J. Toops, Sudhir K. Madan | 2013-02-19 |
| 7684274 | High performance, area efficient direct bitline sensing circuit | Santhana Rengarajan | 2010-03-23 |
| 7568118 | Deterministic operation of an input/output interface | Warren Anderson, Maurice B. Steinman, Richard Marc Watson, Horst Wagner, Christopher C. Gianos +1 more | 2009-07-28 |
| 7349285 | Dual port memory unit using a single port memory core | Lakshmikantha V. Holla, Bryan Sheffield | 2008-03-25 |
| 7015727 | Generating a lock signal indicating whether an output clock signal generated by a PLL is in lock with an input reference signal | — | 2006-03-21 |
| 7016245 | Tracking circuit enabling quick/accurate retrieval of data stored in a memory array | Stephen Wayne Spriggs, Bryan Sheffield, Mohan Mishra | 2006-03-21 |
| 7012846 | Sense amplifier for a memory array | Stephen Wayne Spriggs, Bryan Sheffield, Mohan Mishra | 2006-03-14 |