Issued Patents All Time
Showing 25 most recent of 26 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12334146 | Power loss reduction in data storage arrays | Ajay Bhatia, Sneha Sindhu Matam, Raymond Chang | 2025-06-17 |
| 11870442 | Hybrid pulse/two-stage data latch | Raghava Rao V. Denduluri, Ajay Bhatia, Suparn Vats, Suresh Balasubramanian, Gopinath Venkatesh +1 more | 2024-01-09 |
| 11579642 | Power down detection for non-destructive isolation signal generation | Ajay Bhatia | 2023-02-14 |
| 11496120 | Flip-flop circuit with glitch protection | Qi Ye, Ajay Bhatia | 2022-11-08 |
| 11424734 | Low voltage clock swing tolerant sequential circuits for dynamic power savings | Ajay Bhatia, Qi Ye | 2022-08-23 |
| 11418173 | Hybrid pulse/two-stage data latch | Raghava Rao V. Denduluri, Ajay Bhatia, Suparn Vats, Suresh Balasubramanian, Gopinath Venkatesh +1 more | 2022-08-16 |
| 11418174 | Efficient retention flop utilizing different voltage domain | Greg M. Hess, Victor Zyuban | 2022-08-16 |
| 11336272 | Low power single retention pin flip-flop with balloon latch | Qi Ye | 2022-05-17 |
| 11303268 | Semi dynamic flop and single stage pulse flop with shadow latch and transparency on both input data edges | Ajay Bhatia | 2022-04-12 |
| 11258446 | No-enable setup clock gater based on pulse | Shuyan Lei, Wenhao Li, Hemangi Umakant Gajjewar | 2022-02-22 |
| 11164611 | Level-shifting transparent window sense amplifier | Ajay Bhatia | 2021-11-02 |
| 11139803 | Low power flip-flop with balanced clock-to-Q delay | Ajay Bhatia | 2021-10-05 |
| 11132010 | Power down detection for non-destructive isolation signal generation | Ajay Bhatia | 2021-09-28 |
| 11018653 | Low voltage clock swing tolerant sequential circuits for dynamic power savings | Ajay Bhatia, Qi Ye | 2021-05-25 |
| 11005459 | Efficient retention flop utilizing different voltage domain | Greg M. Hess, Victor Zyuban | 2021-05-11 |
| 10903824 | Pulsed level shifter circuitry | Ajay Bhatia, Wenhao Li | 2021-01-26 |
| 10838483 | Level shifter with isolation on both input and output domains with enable from both domains | Michael R. Seningen, Ajay Bhatia | 2020-11-17 |
| 10742201 | Hybrid pulse/master-slave data latch | Raghava Rao V. Denduluri, Ajay Bhatia, Suparn Vats, Suresh Balasubramanian, Gopinath Venkatesh +1 more | 2020-08-11 |
| 10734040 | Level-shifting transparent window sense amplifier | Ajay Bhatia | 2020-08-04 |
| 10732693 | Hybrid power switch | Ajay Bhatia | 2020-08-04 |
| 10581412 | Pulsed level shifter circuitry | Ajay Bhatia, Wenhao Li | 2020-03-03 |
| 10491197 | Flop circuit with integrated clock gating circuit | Michael R. Seningen, Ajay Bhatia | 2019-11-26 |
| 10461747 | Low power clock gating circuit | Michael R. Seningen, Ajay Bhatia | 2019-10-29 |
| 10270433 | Master-slave clock generation circuit | — | 2019-04-23 |
| 10261563 | Hybrid power switch | Ajay Bhatia | 2019-04-16 |