Issued Patents All Time
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12395174 | Clock-free serialization of asynchronous signals | Victor Zyuban, Ajay Bhatia | 2025-08-19 |
| 11258446 | No-enable setup clock gater based on pulse | Vivekanandan Venugopal, Shuyan Lei, Wenhao Li | 2022-02-22 |
| 10908663 | Power switch multiplexer with configurable overlap | Victor Zyuban, Greg M. Hess | 2021-02-02 |
| 10833664 | Supply tracking delay element in multiple power domain designs | Greg M. Hess, Sachmanik Cheema | 2020-11-10 |
| 10453505 | Pulsed sub-VDD precharging of a bit line | Greg M. Hess | 2019-10-22 |
| 8830783 | Improving read stability of a semiconductor memory | Sachin Satish Idgunji, Vincent Phillipe Schuppe, Yew Keong Chong, Hsin-Yu Chen | 2014-09-09 |
| 8582389 | Write assist in a dual write line semiconductor memory | Sachin Satish Idgunji, Gus Yeung | 2013-11-12 |
| 8479033 | Power supply detection circuitry and method | Gus Yeung | 2013-07-02 |
| 8456199 | Reducing current leakage in a semiconductor device | Gus Yeung | 2013-06-04 |
| 8355276 | Controlling voltage levels applied to access devices when accessing storage cells in a memory | Sachin Satish Idgunji, Gus Yeung | 2013-01-15 |
| 8004913 | Redundancy architecture for an integrated circuit memory | Karl L. Wang | 2011-08-23 |
| 7924638 | Redundancy architecture for an integrated circuit memory | Karl L. Wang | 2011-04-12 |
| 7606057 | Metal line layout in a memory cell | Karl L. Wang | 2009-10-20 |
| 7523420 | Degeneration technique for designing memory devices | Ingming Chang, Jungtae Kwon, Cezary Pietrzyk, Moon-Hae Son | 2009-04-21 |
| 7324368 | Integrated circuit memory with write assist | Karl L. Wang | 2008-01-29 |