| 12333357 |
Memory bit cell for in-memory computation |
Michael A. Dreesen, Ajay Bhatia, Michael R. Seningen, Siddhesh Gaiki |
2025-06-17 |
|
| 12072810 |
System control using sparse data |
Michael R. Seningen, Ben D. Jarrett, Edward M. McCombs |
2024-08-27 |
$283,265,000 |
| 11803480 |
System control using sparse data |
Michael R. Seningen, Ben D. Jarrett, Edward M. McCombs |
2023-10-31 |
$267,879,000 |
| 11418174 |
Efficient retention flop utilizing different voltage domain |
Vivekanandan Venugopal, Victor Zyuban |
2022-08-16 |
$228,519,000 |
| 11327896 |
System control using sparse data |
Michael R. Seningen, Ben D. Jarrett, Edward M. McCombs |
2022-05-10 |
$259,428,000 |
| 11005459 |
Efficient retention flop utilizing different voltage domain |
Vivekanandan Venugopal, Victor Zyuban |
2021-05-11 |
$296,431,000 |
| 10908663 |
Power switch multiplexer with configurable overlap |
Victor Zyuban, Hemangi Umakant Gajjewar |
2021-02-02 |
$228,514,000 |
| 10833664 |
Supply tracking delay element in multiple power domain designs |
Hemangi Umakant Gajjewar, Sachmanik Cheema |
2020-11-10 |
$401,431,000 |
| 10691610 |
System control using sparse data |
Michael R. Seningen, Ben D. Jarrett, Edward M. McCombs |
2020-06-23 |
$111,648,000 |
| 10523194 |
Low leakage power switch |
Jaroslav Raszka, Amrinder S. Barn, Victor Zyuban, Shingo Suzuki, Ajay Bhatia +2 more |
2019-12-31 |
$109,024,000 |
| 10453505 |
Pulsed sub-VDD precharging of a bit line |
Hemangi Umakant Gajjewar |
2019-10-22 |
$134,663,000 |
| 10217494 |
Global bit line pre-charging and data latching in multi-banked memories using a delayed reset latch |
Bharan Giridhar, Sachmanik Cheema |
2019-02-26 |
$103,017,000 |
| 9529533 |
Power grid segmentation for memory arrays |
Michael A. Dreesen, Naveen Javarappa, Ajay Bhatia |
2016-12-27 |
$55,003,000 |
| 9455000 |
Shared gate fed sense amplifier |
Ramesh Arvapalli |
2016-09-27 |
$72,288,000 |
| 9389635 |
Selectable phase or cycle jitter detector |
James E. Burnette, II |
2016-07-12 |
$81,101,000 |
| 9311967 |
Configurable voltage reduction for register file |
Ajay Bhatia, Anshul Y. Mehta, Amrinder S. Barn |
2016-04-12 |
$59,139,000 |
| 9286971 |
Method and circuits for low latency initialization of static random access memory |
Ramesh Arvapalli, Andrew L. Arengo |
2016-03-15 |
$68,647,000 |
| 9236100 |
Dynamic global memory bit line usage as storage node |
Ramesh Arvapalli |
2016-01-12 |
$83,071,000 |
| 9230690 |
Register file write ring oscillator |
James E. Burnette, II |
2016-01-05 |
$62,283,000 |
| 9207705 |
Selectable phase or cycle jitter detector |
James E. Burnette, II |
2015-12-08 |
$55,372,000 |
| 9131899 |
Efficient handling of misaligned loads and stores |
Hari Kannan, Pradeep Kanapathipillai |
2015-09-15 |
$55,353,000 |
| 9001593 |
Apparatus to suppress concurrent read and write word line access of the same memory element in a memory array |
Hitesh Gupta, Aravind Kandala |
2015-04-07 |
$95,745,000 |
| 8988957 |
Sense amplifier soft-fail detection circuit |
James E. Burnette, II |
2015-03-24 |
$60,606,000 |
| 8912853 |
Dynamic level shifter circuit and ring oscillator using the same |
James E. Burnette, II, Shinye Shiu |
2014-12-16 |
$74,972,000 |
| 8860464 |
Zero keeper circuit with full design-for-test coverage |
Hitesh Gupta, Naveen Javarappa |
2014-10-14 |
$68,029,000 |
