Issued Patents All Time
Showing 25 most recent of 40 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12333357 | Memory bit cell for in-memory computation | Michael A. Dreesen, Ajay Bhatia, Michael R. Seningen, Siddhesh Gaiki | 2025-06-17 |
| 12072810 | System control using sparse data | Michael R. Seningen, Ben D. Jarrett, Edward M. McCombs | 2024-08-27 |
| 11803480 | System control using sparse data | Michael R. Seningen, Ben D. Jarrett, Edward M. McCombs | 2023-10-31 |
| 11418174 | Efficient retention flop utilizing different voltage domain | Vivekanandan Venugopal, Victor Zyuban | 2022-08-16 |
| 11327896 | System control using sparse data | Michael R. Seningen, Ben D. Jarrett, Edward M. McCombs | 2022-05-10 |
| 11005459 | Efficient retention flop utilizing different voltage domain | Vivekanandan Venugopal, Victor Zyuban | 2021-05-11 |
| 10908663 | Power switch multiplexer with configurable overlap | Victor Zyuban, Hemangi Umakant Gajjewar | 2021-02-02 |
| 10833664 | Supply tracking delay element in multiple power domain designs | Hemangi Umakant Gajjewar, Sachmanik Cheema | 2020-11-10 |
| 10691610 | System control using sparse data | Michael R. Seningen, Ben D. Jarrett, Edward M. McCombs | 2020-06-23 |
| 10523194 | Low leakage power switch | Jaroslav Raszka, Amrinder S. Barn, Victor Zyuban, Shingo Suzuki, Ajay Bhatia +2 more | 2019-12-31 |
| 10453505 | Pulsed sub-VDD precharging of a bit line | Hemangi Umakant Gajjewar | 2019-10-22 |
| 10217494 | Global bit line pre-charging and data latching in multi-banked memories using a delayed reset latch | Bharan Giridhar, Sachmanik Cheema | 2019-02-26 |
| 9529533 | Power grid segmentation for memory arrays | Michael A. Dreesen, Naveen Javarappa, Ajay Bhatia | 2016-12-27 |
| 9455000 | Shared gate fed sense amplifier | Ramesh Arvapalli | 2016-09-27 |
| 9389635 | Selectable phase or cycle jitter detector | James E. Burnette, II | 2016-07-12 |
| 9311967 | Configurable voltage reduction for register file | Ajay Bhatia, Anshul Y. Mehta, Amrinder S. Barn | 2016-04-12 |
| 9286971 | Method and circuits for low latency initialization of static random access memory | Ramesh Arvapalli, Andrew L. Arengo | 2016-03-15 |
| 9236100 | Dynamic global memory bit line usage as storage node | Ramesh Arvapalli | 2016-01-12 |
| 9230690 | Register file write ring oscillator | James E. Burnette, II | 2016-01-05 |
| 9207705 | Selectable phase or cycle jitter detector | James E. Burnette, II | 2015-12-08 |
| 9131899 | Efficient handling of misaligned loads and stores | Hari Kannan, Pradeep Kanapathipillai | 2015-09-15 |
| 9001593 | Apparatus to suppress concurrent read and write word line access of the same memory element in a memory array | Hitesh Gupta, Aravind Kandala | 2015-04-07 |
| 8988957 | Sense amplifier soft-fail detection circuit | James E. Burnette, II | 2015-03-24 |
| 8912853 | Dynamic level shifter circuit and ring oscillator using the same | James E. Burnette, II, Shinye Shiu | 2014-12-16 |
| 8860464 | Zero keeper circuit with full design-for-test coverage | Hitesh Gupta, Naveen Javarappa | 2014-10-14 |