Issued Patents All Time
Showing 26–40 of 40 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8570788 | Method and apparatus for power domain isolation during power down | Naveen Javarappa | 2013-10-29 |
| 8558603 | Multiplexer with level shifter | Naveen Javarappa, James E. Burnette, II | 2013-10-15 |
| 8476930 | Level shifter with embedded logic and low minimum voltage | Brian J. Campbell, Vincent R. von Kaenel, Naveen Javarappa | 2013-07-02 |
| 8395954 | Leakage and NBTI reduction technique for memory | Brian J. Campbell, Hang Huang | 2013-03-12 |
| 8203898 | Leakage and NBTI reduction technique for memory | Brian J. Campbell, Hang Huang | 2012-06-19 |
| 8174918 | Passgate for dynamic circuitry | — | 2012-05-08 |
| 8130572 | Low power memory array column redundancy mechanism | — | 2012-03-06 |
| 8102728 | Cache optimizations using multiple threshold voltage transistors | Brian J. Campbell, Hang Huang | 2012-01-24 |
| 8027213 | Mechanism for measuring read current variability of SRAM cells | Ashish R. Jain, Priya Ananthanarayanan, Edgardo F. Klass | 2011-09-27 |
| 8014211 | Keeperless fully complementary static selection circuit | Honkai Tam | 2011-09-06 |
| 7994820 | Level shifter with embedded logic and low minimum voltage | Brian J. Campbell, Vincent R. von Kaenel, Naveen Javarappa | 2011-08-09 |
| 7995410 | Leakage and NBTI reduction technique for memory | Brian J. Campbell, Hang Huang | 2011-08-09 |
| 7834662 | Level shifter with embedded logic and low minimum voltage | Brian J. Campbell, Vincent R. von Kaenel, Naveen Javarappa | 2010-11-16 |
| 7454674 | Digital jitter detector | Edgardo F. Klass, Andrew J. Demas, Ashish R. Jain | 2008-11-18 |
| 7411409 | Digital leakage detector that detects transistor leakage current in an integrated circuit | Edgardo F. Klass, Andrew J. Demas, Ashish R. Jain | 2008-08-12 |