| 12395174 |
Clock-free serialization of asynchronous signals |
Victor Zyuban, Hemangi Umakant Gajjewar |
2025-08-19 |
|
| 12379899 |
Performing multiple bit computation and convolution in memory |
Shahzad Nazar, Bharan Giridhar, Mohamed H. Abu-Rahma, Mayur Joshi, Yildiz Sinangil +1 more |
2025-08-05 |
|
| 12333357 |
Memory bit cell for in-memory computation |
Michael A. Dreesen, Michael R. Seningen, Greg M. Hess, Siddhesh Gaiki |
2025-06-17 |
|
| 12334146 |
Power loss reduction in data storage arrays |
Vivekanandan Venugopal, Sneha Sindhu Matam, Raymond Chang |
2025-06-17 |
|
| 11914973 |
Performing multiple bit computation and convolution in memory |
Shahzad Nazar, Bharan Giridhar, Mohamed H. Abu-Rahma, Mayur Joshi, Yildiz Sinangil +1 more |
2024-02-27 |
$182,166,000 |
| 11870442 |
Hybrid pulse/two-stage data latch |
Vivekanandan Venugopal, Raghava Rao V. Denduluri, Suparn Vats, Suresh Balasubramanian, Gopinath Venkatesh +1 more |
2024-01-09 |
$219,732,000 |
| 11579642 |
Power down detection for non-destructive isolation signal generation |
Vivekanandan Venugopal |
2023-02-14 |
$222,931,000 |
| 11496120 |
Flip-flop circuit with glitch protection |
Qi Ye, Vivekanandan Venugopal |
2022-11-08 |
$276,486,000 |
| 11424734 |
Low voltage clock swing tolerant sequential circuits for dynamic power savings |
Vivekanandan Venugopal, Qi Ye |
2022-08-23 |
$220,432,000 |
| 11418173 |
Hybrid pulse/two-stage data latch |
Vivekanandan Venugopal, Raghava Rao V. Denduluri, Suparn Vats, Suresh Balasubramanian, Gopinath Venkatesh +1 more |
2022-08-16 |
$228,519,000 |
| 11303268 |
Semi dynamic flop and single stage pulse flop with shadow latch and transparency on both input data edges |
Vivekanandan Venugopal |
2022-04-12 |
$201,337,000 |
| 11164611 |
Level-shifting transparent window sense amplifier |
Vivekanandan Venugopal |
2021-11-02 |
$262,399,000 |
| 11139803 |
Low power flip-flop with balanced clock-to-Q delay |
Vivekanandan Venugopal |
2021-10-05 |
$251,870,000 |
| 11132010 |
Power down detection for non-destructive isolation signal generation |
Vivekanandan Venugopal |
2021-09-28 |
$352,851,000 |
| 11018653 |
Low voltage clock swing tolerant sequential circuits for dynamic power savings |
Vivekanandan Venugopal, Qi Ye |
2021-05-25 |
$283,400,000 |
| 10903824 |
Pulsed level shifter circuitry |
Vivekanandan Venugopal, Wenhao Li |
2021-01-26 |
$257,028,000 |
| 10838483 |
Level shifter with isolation on both input and output domains with enable from both domains |
Vivekanandan Venugopal, Michael R. Seningen |
2020-11-17 |
$216,835,000 |
| 10742201 |
Hybrid pulse/master-slave data latch |
Vivekanandan Venugopal, Raghava Rao V. Denduluri, Suparn Vats, Suresh Balasubramanian, Gopinath Venkatesh +1 more |
2020-08-11 |
$147,060,000 |
| 10732693 |
Hybrid power switch |
Vivekanandan Venugopal |
2020-08-04 |
$153,818,000 |
| 10734040 |
Level-shifting transparent window sense amplifier |
Vivekanandan Venugopal |
2020-08-04 |
$153,818,000 |
| 10581412 |
Pulsed level shifter circuitry |
Vivekanandan Venugopal, Wenhao Li |
2020-03-03 |
$97,833,000 |
| 10523194 |
Low leakage power switch |
Jaroslav Raszka, Amrinder S. Barn, Victor Zyuban, Shingo Suzuki, Mohamed H. Abu-Rahma +2 more |
2019-12-31 |
$109,024,000 |
| 10491197 |
Flop circuit with integrated clock gating circuit |
Vivekanandan Venugopal, Michael R. Seningen |
2019-11-26 |
$106,937,000 |
| 10461747 |
Low power clock gating circuit |
Vivekanandan Venugopal, Michael R. Seningen |
2019-10-29 |
$145,858,000 |
| 10261563 |
Hybrid power switch |
Vivekanandan Venugopal |
2019-04-16 |
$92,511,000 |
