Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11669419 | System and method for performing a failure assessment of an integrated circuit | Zahi S. Abuhamdeh, Nitin Mohan, Kandadi Vasudevan, Tyler Albarran, Peter Rickenbach | 2023-06-06 |
| 11545981 | DLL-based clocking architecture with programmable delay at phase detector inputs | Nitin Mohan | 2023-01-03 |
| 11545987 | Traversing a variable delay line in a deterministic number of clock cycles | Nitin Mohan, Vasudevan Kandadi | 2023-01-03 |
| 11402413 | Droop detection and mitigation | Nitin Mohan | 2022-08-02 |
| 10784871 | Clocking architecture for DVFS with low-frequency DLL locking | Nitin Mohan | 2020-09-22 |
| 10530370 | Glitch-free PLL Multiplexer | Nitin Mohan, Georgios Faldamis | 2020-01-07 |
| 9721627 | Method and apparatus for aligning signals | David Lin, Edward Wade Thoenes | 2017-08-01 |
| 9570128 | Managing skew in data signals | David Lin, Edward Wade Thoenes | 2017-02-14 |
| 9483100 | Method and apparatus for power gating hardware components in a chip device | David A. Carlson | 2016-11-01 |
| 9263151 | Memory interface with selectable evaluation modes | David Lin | 2016-02-16 |
| 8634509 | Synchronized clock phase interpolator | Ethan Crain, Thomas F. Hummel, Scott E. Meninger | 2014-01-21 |
| 7209531 | Apparatus and method for data deskew | Daniel A. Katz, Richard E. Kessler | 2007-04-24 |