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DLL-based clocking architecture with programmable delay at phase detector inputs |
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Traversing a variable delay line in a deterministic number of clock cycles |
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Droop detection and mitigation |
Nitin Mohan |
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Clocking architecture for DVFS with low-frequency DLL locking |
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Glitch-free PLL Multiplexer |
Nitin Mohan, Georgios Faldamis |
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| 9721627 |
Method and apparatus for aligning signals |
David Lin, Edward Wade Thoenes |
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| 9570128 |
Managing skew in data signals |
David Lin, Edward Wade Thoenes |
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| 9483100 |
Method and apparatus for power gating hardware components in a chip device |
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2016-11-01 |
| 9263151 |
Memory interface with selectable evaluation modes |
David Lin |
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Synchronized clock phase interpolator |
Ethan Crain, Thomas F. Hummel, Scott E. Meninger |
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| 7209531 |
Apparatus and method for data deskew |
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