Issued Patents All Time
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11545987 | Traversing a variable delay line in a deterministic number of clock cycles | Nitin Mohan, Thucydides Xanthopoulos | 2023-01-03 |
| 9740807 | Method to measure edge-rate timing penalty of digital integrated circuits | Nitin Mohan | 2017-08-22 |
| 9601181 | Controlled multi-step de-alignment of clocks | David Lin, Edward Wade Thoenes | 2017-03-21 |