Issued Patents All Time
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11669419 | System and method for performing a failure assessment of an integrated circuit | Nitin Mohan, Kandadi Vasudevan, Thucydides Xanthopoulos, Tyler Albarran, Peter Rickenbach | 2023-06-06 |
| 9344075 | Measuring delay between signal edges of different signals using an undersampling clock | Michael Ricchetti, Richard Lombard | 2016-05-17 |
| 7714565 | Methods and apparatus for testing delay locked loops and clock skew | Vincent D'Alessandro | 2010-05-11 |
| 7355380 | Methods and apparatus for testing delay locked loops and clock skew | Vincent D'Alessandro | 2008-04-08 |
| 6219775 | Massively parallel computer including auxiliary vector processor | Jon P. Wade, Daniel R. Cassiday, Robert D. Lordi, Guy L. Steele, Jr., Margaret A. St. Pierre +8 more | 2001-04-17 |
| 5872987 | Massively parallel computer including auxiliary vector processor | Jon P. Wade, Daniel R. Cassiday, Robert D. Lordi, Guy L. Steele, Jr., Margaret A. St. Pierre +8 more | 1999-02-16 |
| 5118975 | Digital clock buffer circuit providing controllable delay | W. Daniel Hillis, Bradley C. Kuszmaul, Jon P. Wade, Shaw-Wen Yang | 1992-06-02 |