Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12314106 | Operating voltage adjustment for aging circuits | Sriram Sambamurthy, Sriram Sundaram, Indrani Paul, Larry D. Hewitt, Anil Harwani +4 more | 2025-05-27 |
| 12298829 | Platform power manager for rack level power and thermal constraints | Indrani Paul, Sriram Sambamurthy, Larry D. Hewitt, Kevin M. Lepak, Samuel D. Naffziger +6 more | 2025-05-13 |
| 11829222 | Operating voltage adjustment for aging circuits | Sriram Sambamurthy, Sriram Sundaram, Indrani Paul, Larry D. Hewitt, Anil Harwani +4 more | 2023-11-28 |
| 11703930 | Platform power manager for rack level power and thermal constraints | Indrani Paul, Sriram Sambamurthy, Larry D. Hewitt, Kevin M. Lepak, Samuel D. Naffziger +6 more | 2023-07-18 |
| 11073888 | Platform power manager for rack level power and thermal constraints | Indrani Paul, Sriram Sambamurthy, Larry D. Hewitt, Kevin M. Lepak, Samuel D. Naffziger +6 more | 2021-07-27 |
| 10060955 | Calibrating power supply voltages using reference measurements from code loop executions | Robert A. Hershberger, Sriram Sambamurthy, Samuel D. Naffziger, Christopher E. Tressler, Sho-Chien Kang +6 more | 2018-08-28 |
| 9621143 | Propagation simulation buffer for clock domain crossing | Michael J. Osborn, Michael J. Tresidder, Joseph Kidd, Priyank Parakh, Steven J. Kommrusch | 2017-04-11 |
| 9372499 | Low insertion delay clock doubler and integrated circuit clock distribution system using same | Sriram Sambamurthy, Arun Sundaresan Iyer, Alok Baluni | 2016-06-21 |
| 8595563 | Method and circuitry for debugging a power-gated circuit | Benjamin Tsien, Kiran Bondalapati, Hao Huang, William A. Hughes, Eric M. Rentschler +1 more | 2013-11-26 |
| 8584067 | Clock domain crossing buffer | Michael J. Osborn, Michael J. Tresidder, Joseph Kidd, Priyank Parakh, Steven J. Kommrusch | 2013-11-12 |
| 8381163 | Power-gated retention flops | Jeremy Schreiber | 2013-02-19 |