Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11881862 | Mitigation of duty-cycle distortion | Udayakiran Kumar Yallamaraju, Xia Li, Pankaj Deshmukh, Vajram Ghantasala, Bin Yang +4 more | 2024-01-23 |
| 10805643 | Adaptive error-controlled dynamic voltage and frequency scaling for low power video codecs | Ihab Amer, Gabor Sines, Khaled Mammou, Haibo Liu | 2020-10-13 |
| 10247770 | Gate oxide soft breakdown detection circuit | Abhay Deshpande, Prasanth K. Vallur, Girish Anathahally Singrigowda, Stephen V. Kosonocky | 2019-04-02 |
| 9639488 | Encoding valid data states in source synchronous bus interfaces using clock signal transitions | Gregory Sadowski, Sudha Thiruvengadam | 2017-05-02 |
| 9494649 | Adaptive digital delay line for characterization of clock uncertainties | Prashanth Vallur, Shraddha Padiyar, Amit Prakash Govil | 2016-11-15 |
| 9372499 | Low insertion delay clock doubler and integrated circuit clock distribution system using same | Sriram Sambamurthy, Alok Baluni, Aaron Joseph Grenat | 2016-06-21 |
| 9319037 | Self-adjusting clock doubler and integrated circuit clock distribution system using same | Alok Baluni, Samuel D. Naffziger, Sriram Sambamurthy | 2016-04-19 |
| 8593177 | Integrated circuit with timing aware clock-tree and method for designing such an integrated circuit | Nithin Shetty Kidiyoor, Shyam Sundaramoorthy, Ravishankar Karthikeyan | 2013-11-26 |
| 8584065 | Method and apparatus for designing an integrated circuit | Yousuff Mohammed Shariff | 2013-11-12 |
| 8504866 | Supplying hysteresis effect mitigated clock signals based on silicon-test characterized parameter | Bhawna Tomar, Animesh Jain, Krishna Sethupathy Leela | 2013-08-06 |
| 8120406 | Sequential circuit with dynamic pulse width control | Shibashish Patel, Animesh Jain | 2012-02-21 |