Issued Patents All Time
Showing 1–25 of 35 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9686536 | Method and apparatus for aggregation and streaming of monitoring data | Sebastien Nussbaum | 2017-06-20 |
| 9442815 | Distributed on-chip debug triggering with allocated bus lines | Scott P. Nixon | 2016-09-13 |
| 9329963 | Debug apparatus and methods for dynamically switching power domains | Shantanu Sarangi, Christian Warling, Vikram Chopra, Mihir Shaileshbhai Doctor | 2016-05-03 |
| 9262293 | Debug apparatus and methods for dynamically switching power domains | Shantanu Sarangi, Rahul Dev, Vikram Chopra, Mihir Shaileshbhai Doctor | 2016-02-16 |
| 9129061 | Method and apparatus for on-chip debugging | Scott P. Nixon, Tiger Lu | 2015-09-08 |
| 9037911 | Debug state machines and methods of their operation | Steven J. Kommrusch, Scott P. Nixon | 2015-05-19 |
| 8959398 | Multiple clock domain debug capability | Scott P. Nixon | 2015-02-17 |
| 8935574 | Correlating traces in a computing system | Ryan D. Bedwell, Elizabeth M. Cooper | 2015-01-13 |
| 8832500 | Multiple clock domain tracing | Scott P. Nixon | 2014-09-09 |
| 8683265 | Debug state machine cross triggering | Steven J. Kommrusch, Elizabeth M. Cooper, Stephen C. Ennis | 2014-03-25 |
| 8595563 | Method and circuitry for debugging a power-gated circuit | Benjamin Tsien, Kiran Bondalapati, Hao Huang, William A. Hughes, Jeremy Schreiber +1 more | 2013-11-26 |
| 8566645 | Debug state machine and processor including the same | Steven J. Kommrusch, Scott P. Nixon | 2013-10-22 |
| 7533285 | Synchronizing link delay measurement over serial links | Samuel D. Naffziger | 2009-05-12 |
| 7506130 | Mirrored computer memory on split bus | Darel N. Emmot | 2009-03-17 |
| 7426596 | Integrated circuit with a scalable high-bandwidth architecture | Darel N. Emmot, Michael Tayler | 2008-09-16 |
| 7289587 | Repeatability over communication links | Samuel D. Naffziger | 2007-10-30 |
| 7103790 | Memory controller driver circuitry having a multiplexing stage to provide data to at least N-1 of N data propagation circuits, and having output merging circuitry to alternately couple the N data propagation circuits to a data pad to generate either a 1x or Mx stream of data | Jeffrey G. Hargis, Leith L. Johnson | 2006-09-05 |
| 7103826 | Memory system and controller for same | Larry J. Thayer, Michael Tayler | 2006-09-05 |
| 7103793 | Memory controller having receiver circuitry capable of alternately generating one or more data streams as data is received at a data pad, in response to counts of strobe edges received at a strobe pad | Jeffrey G. Hargis, George Thomas Letey, Leith L. Johnson | 2006-09-05 |
| 7099994 | RAID memory system | Larry J. Thayer, Michael Tayler | 2006-08-29 |
| 6990562 | Memory controller to communicate with memory devices that are associated with differing data/strobe ratios | Jeffrey G. Hargis, George Thomas Letey | 2006-01-24 |
| 6930932 | Data signal reception latch control using clock aligned relative to strobe signal | — | 2005-08-16 |
| 6889335 | Memory controller receiver circuitry with tri-state noise immunity | Jeffrey G. Hargis, Leith L. Johnson | 2005-05-03 |
| 6788135 | Terminating pathway for a clock signal | Lisa Ann Yunker, Peter Moldauer | 2004-09-07 |
| 6678811 | Memory controller with 1X/MX write capability | Jeffrey G. Hargis, Leith L. Johnson | 2004-01-13 |