Issued Patents All Time
Showing 26–35 of 35 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6633965 | Memory controller with 1×/M× read capability | Jeffrey G. Hargis, Leith L. Johnson | 2003-10-14 |
| 6625702 | Memory controller with support for memory modules comprised of non-homogeneous data width RAM devices | Jeffrey G. Hargis, George Thomas Letey | 2003-09-23 |
| 6381663 | Mechanism for implementing bus locking with a mixed architecture | John A. Morrison, Robert J. Blakely, John R. Feehrer | 2002-04-30 |
| 6360301 | Coherency protocol for computer cache | Blaine D. Gaither | 2002-03-19 |
| 5969726 | Caching and coherency control of multiple geometry accelerators in a computer graphics system | Alan S. Krech, Jr. | 1999-10-19 |
| 5940086 | System and method for dynamically allocating data among geometry accelerators in a computer graphics system | Alan S. Krech, Jr., Noel D. Scott | 1999-08-17 |
| 5920326 | Caching and coherency control of multiple geometry accelerators in a computer graphics system | Alan S. Krech, Jr., Kendall F Tidwell | 1999-07-06 |
| 5821950 | Computer graphics system utilizing parallel processing for enhanced performance | Monish Shah, Mary Anne R. Matthews, Alan S. Krech, Jr., Erin A. Handgen | 1998-10-13 |
| 5793660 | Circuit for finding m modulo n | — | 1998-08-11 |
| 5671373 | Data bus protocol for computer graphics system | Bryan G. Prouty | 1997-09-23 |