Issued Patents All Time
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11030061 | Single and double chip spare | Gary Gostin | 2021-06-08 |
| 10585598 | Modifying accessibility based on memory access patterns | Andrew Brown, Bryan Stiekes | 2020-03-10 |
| 10468118 | DRAM row sparing | Andrew C. Walton, Melvin K. Benedict, Eric L. Pope | 2019-11-05 |
| 10379971 | Single and double chip space | Gary Gostin | 2019-08-13 |
| 9778982 | Memory erasure information in cache lines | Lidia Warnes, Andrew C. Walton | 2017-10-03 |
| 9690673 | Single and double chip spare | Gary Gostin | 2017-06-27 |
| 8429376 | Translation look-aside buffer | — | 2013-04-23 |
| 8244983 | Memory control systems with directory caches and methods for operation thereof | — | 2012-08-14 |
| 7941610 | Coherency directory updating in a multiprocessor computing system | Patrick Knebel | 2011-05-10 |
| 7818508 | System and method for achieving enhanced memory access capabilities | Bryan Hornung, Gary Gostin, Craig Warner | 2010-10-19 |
| 7624234 | Directory caches, and methods for operation thereof | Leith L. Johnson | 2009-11-24 |
| 7343440 | Integrated circuit with a scalable high-bandwidth architecture | Eri M. Rentschler, Michael Tayler | 2008-03-11 |
| 6901486 | Method and system for optimizing pre-fetch memory transactions | George Thomas Letey | 2005-05-31 |
| 5821950 | Computer graphics system utilizing parallel processing for enhanced performance | Eric M. Rentschler, Monish Shah, Mary Anne R. Matthews, Alan S. Krech, Jr. | 1998-10-13 |
| 5629720 | Display mode processor | Robert W. Cherry, Brad D. Reak | 1997-05-13 |
| 5222243 | Sorting apparatus having plurality of registers with associated multiplexers and comparators for concurrently sorting and storing incoming data according to magnitude | Randall D. Briggs | 1993-06-22 |