Issued Patents All Time
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11444918 | Subsystem firewalls | Douglas L. Stiles, Edmund B. Nightingale | 2022-09-13 |
| 11036654 | NOP sled defense | Felix Stefan Domke, Edmund B. Nightingale | 2021-06-15 |
| 10942798 | Watchdog timer hierarchy | Douglas L. Stiles, Edmund B. Nightingale, Stephen E. Hodges, Philip John Joseph Wright | 2021-03-09 |
| 10783075 | Data security for multiple banks of memory | Douglas L. Stiles, Edmund B. Nightingale | 2020-09-22 |
| 10715526 | Multiple cores with hierarchy of trust | Edmund B. Nightingale, Reuben R. Olinsky, Galen C. Hunt, Douglas L. Stiles | 2020-07-14 |
| 10587575 | Subsystem firewalls | Douglas L. Stiles, Edmund B. Nightingale | 2020-03-10 |
| 10353815 | Data security for multiple banks of memory | Douglas L. Stiles, Edmund B. Nightingale | 2019-07-16 |
| 10346345 | Core mapping | Douglas L. Stiles, Edmund B. Nightingale | 2019-07-09 |
| 7171534 | System and method for multi-modal memory controller system operation | Jeff G. Hargis, Michael Tayler | 2007-01-30 |
| 7103793 | Memory controller having receiver circuitry capable of alternately generating one or more data streams as data is received at a data pad, in response to counts of strobe edges received at a strobe pad | Eric M. Rentschler, Jeffrey G. Hargis, Leith L. Johnson | 2006-09-05 |
| 6990562 | Memory controller to communicate with memory devices that are associated with differing data/strobe ratios | Eric M. Rentschler, Jeffrey G. Hargis | 2006-01-24 |
| 6901486 | Method and system for optimizing pre-fetch memory transactions | Erin A. Handgen | 2005-05-31 |
| 6854043 | System and method for multi-modal memory controller system operation | Jeff G. Hargis, Michael Tayler | 2005-02-08 |
| 6625702 | Memory controller with support for memory modules comprised of non-homogeneous data width RAM devices | Eric M. Rentschler, Jeffrey G. Hargis | 2003-09-23 |