Issued Patents All Time
Showing 1–25 of 31 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9298668 | Bit error rate reduction buffer, method and apparatus | — | 2016-03-29 |
| 9182925 | Memory system that utilizes a wide input/output (I/O) interface to interface memory storage with an interposer | — | 2015-11-10 |
| 8914683 | Repairing high-speed serial links | — | 2014-12-16 |
| 8886892 | Memory module and method employing a multiplexer to replace a memory device | — | 2014-11-11 |
| 8634221 | Memory system that utilizes a wide input/output (I/O) interface to interface memory storage with an interposer and that utilizes a SerDes interface to interface a memory controller with an integrated circuit, and a method | — | 2014-01-21 |
| 8612797 | Systems and methods of selectively managing errors in memory modules | Andrew C. Walton, Mike Cogdill, George Krejci | 2013-12-17 |
| 8554991 | High speed interface for dynamic random access memory (DRAM) | — | 2013-10-08 |
| 8473791 | Redundant memory to mask DRAM failures | Mark Shaw, Chris Petersen, Lidia Warnes, Dheemanth Nagaraj | 2013-06-25 |
| 8386702 | Memory controller | Leith L. Johnson | 2013-02-26 |
| 8352896 | System and method for distribution analysis of stacked-die integrated circuits | — | 2013-01-08 |
| 7996710 | Defect management for a semiconductor memory system | Dheemanth Nagaraj | 2011-08-09 |
| 7975205 | Error correction algorithm selection based upon memory organization | — | 2011-07-05 |
| 7844868 | System and method for implementing a stride value for memory testing | Andrew C. Walton, Mike Cogdill | 2010-11-30 |
| 7783935 | Bit error rate reduction buffer | — | 2010-08-24 |
| 7694193 | Systems and methods for implementing a stride value for accessing memory | Andrew C. Walton, Mike Cogdill | 2010-04-06 |
| 7656727 | Semiconductor memory device and system providing spare memory locations | — | 2010-02-02 |
| 7599235 | Memory correction system and method | — | 2009-10-06 |
| 7539931 | Storage element for mitigating soft errors in logic | — | 2009-05-26 |
| 7307902 | Memory correction system and method | — | 2007-12-11 |
| 7227797 | Hierarchical memory correction system and method | Michael Tayler | 2007-06-05 |
| 7103826 | Memory system and controller for same | Eric M. Rentschler, Michael Tayler | 2006-09-05 |
| 7099994 | RAID memory system | Eric M. Rentschler, Michael Tayler | 2006-08-29 |
| 6943804 | System and method for performing BLTs | Byron A. Alcorn, Ronald D. Larson | 2005-09-13 |
| 6940525 | Method and apparatus for performing a perspective projection in a graphics device of a computer graphics display system | Roland M. Hochmuth, Samuel C. Sands, Gayani N. K. Gamage | 2005-09-06 |
| 6876224 | Method and apparatus for high speed bus having adjustable, symmetrical, edge-rate controlled, waveforms | David J. Marshall, Philip Lionel Barnes | 2005-04-05 |