Issued Patents All Time
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8612797 | Systems and methods of selectively managing errors in memory modules | Larry J. Thayer, Andrew C. Walton, George Krejci | 2013-12-17 |
| 7844868 | System and method for implementing a stride value for memory testing | Larry J. Thayer, Andrew C. Walton | 2010-11-30 |
| 7694193 | Systems and methods for implementing a stride value for accessing memory | Larry J. Thayer, Andrew C. Walton | 2010-04-06 |
| 7307862 | Circuit and system for accessing memory modules | Idis Ramona Martinez, Derek Schumacher | 2007-12-11 |
| 7054179 | Double-high memory system compatible with termination schemes for single-high memory systems | Idis Ramona Martinez, Derek Schumacher | 2006-05-30 |