Issued Patents All Time
Showing 25 most recent of 56 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12278598 | Parallelized low noise amplifiers for a quantum computer | Mridula Prathapan, Thomas Morf, Peter Mueller, Bogdan Cezar Zota, Pier Andrea Francese | 2025-04-15 |
| 12095473 | Time domain interleaving | Abdullah Serdar Yonar, Pier Andrea Francese, Mridula Prathapan, Matthias Braendli, Thomas Morf | 2024-09-17 |
| 12088316 | Successive-approximation analog-to-digital converters | Abdullah Serdar Yonar, Pier Andrea Francese | 2024-09-10 |
| 12088314 | Segmented digital-to-analog converter wireline driver | Martin Cochet, John F. Bulzacchelli, Timothy O. Dickson, Zeynep Toprak-Deniz | 2024-09-10 |
| 11916568 | Sampling circuit with a hierarchical time step generator | Pier Andrea Francese, Abdullah Serdar Yonar, Mridula Prathapan, Thomas Morf | 2024-02-27 |
| 11816062 | Control unit for qubits | Thomas Morf, Cezar Bogdan Zota, Peter Mueller, Pier Andrea Francese, Matthias Braendli +1 more | 2023-11-14 |
| 11811418 | Analog-to-digital converter circuit with a nested look up table | Pier Andrea Francese, Abdullah Serdar Yonar, Mridula Prathapan, Thomas Morf | 2023-11-07 |
| 11652493 | Successive-approximation analog-to-digital converters | Abdullah Serdar Yonar, Pier Andrea Francese | 2023-05-16 |
| 11621720 | Quantum processing apparatus with downsampling analog-to-digital converter | Peter Mueller, Thomas Morf, Pier Andrea Francese | 2023-04-04 |
| 11271550 | Synchronous divider based on cascaded retiming | Pier Andrea Francese, Mridula Prathapan, Abdullah Serdar Yonar | 2022-03-08 |
| 11205131 | Sequence detection | Hazar Yüksel, Giovanni Cherubini, Roy D. Cideciyan, Simeon Furrer | 2021-12-21 |
| 11095487 | Operating a wireline receiver with a tunable timing characteristic | Abdullah Serdar Yonar, Pier Andrea Francese | 2021-08-17 |
| 11057039 | Clock divider with quadrature error correction | Vishal Khatri, Pier Andrea Francese, Matthias Braendli | 2021-07-06 |
| 10943653 | Memory receiver with resistive voltage divider | — | 2021-03-09 |
| 10720994 | PAM-4 transmitter precoder for 1+0.5D PR channels | Alessandro Cevrero, Pier Andrea Francese, Christian I. Menolfi, Ilter Özkaya, Thomas H. Toifl | 2020-07-21 |
| 10680860 | Method and apparatus for generating a multi-level pseudo-random test signal | — | 2020-06-09 |
| 10541691 | Bang-bang phase detectors | Pier Andrea Francese, Thomas H. Toifl | 2020-01-21 |
| 10454723 | Decision feedback equalizer | Vishal Khatri | 2019-10-22 |
| 10256845 | Symbol timing recovery based on speculative tentative symbol decisions | Hazar Yüksel, Giovanni Cherubini, Roy D. Cideciyan, Simeon Furrer | 2019-04-09 |
| 10237098 | Method and apparatus for generating a multi-level pseudo-random test signal | — | 2019-03-19 |
| 10205525 | PAM-4 transmitter precoder for 1+0.5D PR channels | Alessandro Cevrero, Pier Andrea Francese, Christian I. Menolfi, Ilter Özkaya, Thomas H. Toifl | 2019-02-12 |
| 10078342 | Low dropout voltage regulator with variable load compensation | — | 2018-09-18 |
| 9991990 | Sequence detection | Giovanni Cherubini, Roy D. Cideciyan, Simeon Furrer, Hazar Yüksel | 2018-06-05 |
| 9928035 | Multiply-and-accumulate unit in carry-save adder format and application in a feedback loop equalizer | — | 2018-03-27 |
| 9882752 | Method and apparatus for generating a multi-level pseudo-random test signal | — | 2018-01-30 |