Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10141915 | Sequenced pulse-width adjustment in a resonant clocking circuit | Thomas J. Bucelot, Phillip J. Restle | 2018-11-27 |
| 9705479 | Sequenced pulse-width adjustment in a resonant clocking circuit | Thomas J. Bucelot, Phillip J. Restle | 2017-07-11 |
| 9634654 | Sequenced pulse-width adjustment in a resonant clocking circuit | Thomas J. Bucelot, Phillip J. Restle | 2017-04-25 |
| 9618966 | Pulse-drive resonant clock with on-the-fly mode change | Thomas J. Bucelot, Robert L. Franch, Phillip J. Restle, Christos Vezyrtzis | 2017-04-11 |
| 9612614 | Pulse-drive resonant clock with on-the-fly mode change | Thomas J. Bucelot, Robert L. Franch, Phillip J. Restle, Christos Vezyrtzis | 2017-04-04 |
| 9575119 | Measurement of signal delays in microprocessor integrated circuits with sub-picosecond accuracy using frequency stepping | Robert L. Franch, Phillip J. Restle | 2017-02-21 |
| 9571100 | Clock buffers with pulse drive capability for power efficiency | Aditya Bansal, Thomas J. Bucelot, Alan J. Drake, Phillip J. Restle, Mrigank Sharad | 2017-02-14 |
| 9568548 | Measurement of signal delays in microprocessor integrated circuits with sub-picosecond accuracy using frequency stepping | Robert L. Franch, Phillip J. Restle | 2017-02-14 |
| 9276563 | Clock buffers with pulse drive capability for power efficiency | Aditya Bansal, Thomas J. Bucelot, Alan J. Drake, Phillip J. Restle, Mrigank Sharad | 2016-03-01 |
| 8863066 | Wiring-optimal method to route high performance clock nets satisfying electrical and reliability constraints | Joseph N. Kozhaya, Phillip J. Restle | 2014-10-14 |
| 8027798 | Digital thermal sensor test implementation without using main core voltage supply | Charles Ray Johns, Mack W. Riley, Michael Fan Wang | 2011-09-27 |