| 11422611 |
Adaptive frequency optimization in processors |
Bjorn P. Christensen, James M. Crafts, Allen R. Hall, Kevin F. Reick, Jon Robert Tetzloff |
2022-08-23 |
| 10509457 |
Adaptive frequency optimization in processors |
Bjorn P. Christensen, James M. Crafts, Allen R. Hall, Kevin F. Reick, Jon Robert Tetzloff |
2019-12-17 |
| 9575115 |
Methodology of grading reliability and performance of chips across wafer |
James P. Di Sarro, Robert J. Gauthier, Jr., Tom C. Lee, Junjun Li, Souvick Mitra +2 more |
2017-02-21 |
| 9520876 |
Power gating and clock gating in wiring levels |
Tassbieh Hassan, Kirk D. Peterson, John E. Sheets, II, Christine Whiteside |
2016-12-13 |
| 9472269 |
Stress balancing of circuits |
Igor Arsovski, John Bradley Deforge, Ezra D. B. Hall, Kirk D. Peterson |
2016-10-18 |
| 9437670 |
Light activated test connections |
John Bradley Deforge, John J. Ellis-Monaghan, Jeffrey P. Gambino, Ezra D. B. Hall, Marc D. Knox +1 more |
2016-09-06 |
| 9383767 |
Circuit design for balanced logic stress |
Frances S. M. Clougherty, William Paul Hovis, Kirk D. Peterson, Mack W. Riley |
2016-07-05 |
| 9250645 |
Circuit design for balanced logic stress |
Frances S. M. Clougherty, William Paul Hovis, Kirk D. Peterson, Mack W. Riley |
2016-02-02 |
| 9099427 |
Thermal energy dissipation using backside thermoelectric devices |
Jeffrey P. Gambino, Kirk D. Peterson |
2015-08-04 |
| 8943458 |
Determining chip burn-in workload using emulated application condition |
Frances S. M. Clougherty, William Paul Hovis, Kirk D. Peterson, Mack W. Riley |
2015-01-27 |
| 7877222 |
Structure for a phase locked loop with adjustable voltage based on temperature |
David William Boerstler, Eskinder Hailu, Kirk D. Peterson, Jieming Qi |
2011-01-25 |
| 7493229 |
Adjusting voltage for a phase locked loop based on temperature |
David William Boerstler, Eskinder Hailu, Kirk D. Peterson, Jieming Qi |
2009-02-17 |
