Issued Patents All Time
Showing 1–25 of 36 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12027612 | SCR having selective well contacts | Karmel Kranthi Nagothu, Rajkumar Sankaralingam | 2024-07-02 |
| 11532609 | ESD device with fast response and high transient current | Aravind C. Appaswamy | 2022-12-20 |
| 11139292 | Conductivity modulated drain extended MOSFET | Aravind C. Appaswamy, Farzan Farbiz | 2021-10-05 |
| 11114848 | ESD protection charge pump active clamp for low-leakage applications | Farzan Farbiz | 2021-09-07 |
| 10861844 | ESD device with fast response and high transient current | Aravind C. Appaswamy | 2020-12-08 |
| 10763251 | ESD network comprising variable impedance discharge path | Krishna Praveen Mysore Rajagopal, Mariano Dissegna, Lihui Wang, Ann Concannon | 2020-09-01 |
| 10756078 | Structure and method for dynamic biasing to improve ESD robustness of current mode logic (CML) drivers | Robert J. Gauthier, Jr., Nathan Jack, Junjun Li, Souvick Mitra | 2020-08-25 |
| 10529708 | Conductivity modulated drain extended MOSFET | Aravind C. Appaswamy, Farzan Farbiz | 2020-01-07 |
| 10396550 | ESD protection charge pump active clamp for low-leakage applications | Farzan Farbiz | 2019-08-27 |
| 10359461 | Integrated circuit protection during high-current ESD testing | Shunhua T. Chang, Robert J. Gauthier, Jr., Nathan Jack, Souvick Mitra | 2019-07-23 |
| 10249610 | IGBT coupled to a reverse bias device in series | Aravind C. Appaswamy, Krishna Praveen Mysore Rajagopal, Akram A. Salman, Muhammad Yusuf Ali | 2019-04-02 |
| 10181463 | Structure and method for dynamic biasing to improve ESD robustness of current mode logic (CML) drivers | Robert J. Gauthier, Jr., Nathan Jack, Junjun Li, Souvick Mitra | 2019-01-15 |
| 9905558 | Conductivity modulated drain extended MOSFET | Aravind C. Appaswamy, Farzan Farbiz | 2018-02-27 |
| 9869708 | Integrated circuit protection during high-current ESD testing | Shunhua T. Chang, Robert J. Gauthier, Jr., Nathan Jack, Souvick Mitra | 2018-01-16 |
| 9620497 | Structure and method for dynamic biasing to improve ESD robustness of current mode logic (CML) drivers | Robert J. Gauthier, Jr., Nathan Jack, Junjun Li, Souvick Mitra | 2017-04-11 |
| 9575115 | Methodology of grading reliability and performance of chips across wafer | Nathaniel R. Chadwick, Robert J. Gauthier, Jr., Tom C. Lee, Junjun Li, Souvick Mitra +2 more | 2017-02-21 |
| 9536870 | SCR with fin body regions for ESD protection | Robert J. Gauthier, Jr., Tom C. Lee, Junjun Li, Souvick Mitra, Christopher S. Putnam | 2017-01-03 |
| 9435841 | Integrated circuit protection during high-current ESD testing | Shunhua T. Chang, Robert J. Gauthier, Jr., Nathan Jack, Souvick Mitra | 2016-09-06 |
| 9413169 | Electrostatic discharge protection circuit with a fail-safe mechanism | Robert J. Gauthier, Jr., Tom C. Lee, Junjun Li, Souvick Mitra, Christopher S. Putnam | 2016-08-09 |
| 9377496 | Cancellation of secondary reverse reflections in a very-fast transmission line pulse system | Shunhua T. Chang, Robert J. Gauthier, Jr. | 2016-06-28 |
| 9274155 | Cancellation of secondary reverse reflections in a very-fast transmission line pulse system | Shunhua T. Chang, Robert J. Gauthier, Jr. | 2016-03-01 |
| 9263402 | Self-protected metal-oxide-semiconductor field-effect transistor | Robert J. Gauthier, Jr., Junjun Li | 2016-02-16 |
| 9240471 | SCR with fin body regions for ESD protection | Robert J. Gauthier, Jr., Tom C. Lee, Junjun Li, Souvick Mitra, Christopher S. Putnam | 2016-01-19 |
| 9219055 | Structure and method for dynamic biasing to improve ESD robustness of current mode logic (CML) drivers | Robert J. Gauthier, Jr., Nathan Jack, Jun Li, Souvick Mitra | 2015-12-22 |
| 9064786 | Dual three-dimensional (3D) resistor and methods of forming | Robert J. Gauthier, Jr., Tom C. Lee, Junjun Li, Souvick Mitra, Christopher S. Putnam | 2015-06-23 |