NJ

Nathan Jack

IN Intel: 9 patents #4,428 of 30,777Top 15%
IBM: 7 patents #14,640 of 70,183Top 25%
UU Utah State University: 1 patents #122 of 289Top 45%
Overall (All Time): #264,265 of 4,157,543Top 7%
17
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
12402349 Gate-all-around integrated circuit structures having devices with channel-to-substrate electrical contact Biswajeet Guha, William Hsu, Chung-Hsun Lin, Kinyip Phoa, Oleg Golonzka +5 more 2025-08-26
12328947 Substrate-less silicon controlled rectifier (SCR) integrated circuit structures Rui Ma, Kalyan C. Kolluru, Nicholas A. Thomson, Ayan Kar, Benjamin Orr +3 more 2025-06-10
12317590 Substrate-free integrated circuit structures Biswajeet Guha, Brian J. Greene, Avyaya Jayanthinarasimham, Ayan Kar, Benjamin Orr +9 more 2025-05-27
12288789 Gate-all-around integrated circuit structures having devices with source/drain-to-substrate electrical contact Biswajeet Guha, William Hsu, Chung-Hsun Lin, Kinyip Phoa, Oleg Golonzka +5 more 2025-04-29
11908856 Gate-all-around integrated circuit structures having devices with source/drain-to-substrate electrical contact Biswajeet Guha, William Hsu, Chung-Hsun Lin, Kinyip Phoa, Oleg Golonzka +5 more 2024-02-20
11837641 Gate-all-around integrated circuit structures having adjacent deep via substrate contacts for sub-fin electrical contact Biswajeet Guha, William Hsu, Chung-Hsun Lin, Kinyip Phoa, Oleg Golonzka +5 more 2023-12-05
11824116 Gate-all-around integrated circuit structures having devices with channel-to-substrate electrical contact Biswajeet Guha, William Hsu, Chung-Hsun Lin, Kinyip Phoa, Oleg Golonzka +5 more 2023-11-21
11652107 Substrate-less FinFET diode architectures with backside metal contact and subfin regions Nicholas A. Thomson, Ayan Kar, Kalyan C. Kolluru, Rui Ma, Mark Bohr +2 more 2023-05-16
11264405 Semiconductor diodes employing back-side semiconductor or metal Patrick Morrow, Rishabh Mehandru 2022-03-01
10756078 Structure and method for dynamic biasing to improve ESD robustness of current mode logic (CML) drivers James P. Di Sarro, Robert J. Gauthier, Jr., Junjun Li, Souvick Mitra 2020-08-25
10359461 Integrated circuit protection during high-current ESD testing Shunhua T. Chang, James P. Di Sarro, Robert J. Gauthier, Jr., Souvick Mitra 2019-07-23
10181463 Structure and method for dynamic biasing to improve ESD robustness of current mode logic (CML) drivers James P. Di Sarro, Robert J. Gauthier, Jr., Junjun Li, Souvick Mitra 2019-01-15
9869708 Integrated circuit protection during high-current ESD testing Shunhua T. Chang, James P. Di Sarro, Robert J. Gauthier, Jr., Souvick Mitra 2018-01-16
9620497 Structure and method for dynamic biasing to improve ESD robustness of current mode logic (CML) drivers James P. Di Sarro, Robert J. Gauthier, Jr., Junjun Li, Souvick Mitra 2017-04-11
9435841 Integrated circuit protection during high-current ESD testing Shunhua T. Chang, James P. Di Sarro, Robert J. Gauthier, Jr., Souvick Mitra 2016-09-06
9219055 Structure and method for dynamic biasing to improve ESD robustness of current mode logic (CML) drivers James P. Di Sarro, Robert J. Gauthier, Jr., Jun Li, Souvick Mitra 2015-12-22
7831205 Methods and systems for wireless communication by magnetic induction Krishna Shenai 2010-11-09