Issued Patents All Time
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10636872 | Apparatus and method to prevent integrated circuit from entering latch-up mode | Ephrem G. Gebreselasie, Mujahid Muhammad, Xiangxiang Lu, Mickey H. Yu | 2020-04-28 |
| 10359461 | Integrated circuit protection during high-current ESD testing | James P. Di Sarro, Robert J. Gauthier, Jr., Nathan Jack, Souvick Mitra | 2019-07-23 |
| 9869708 | Integrated circuit protection during high-current ESD testing | James P. Di Sarro, Robert J. Gauthier, Jr., Nathan Jack, Souvick Mitra | 2018-01-16 |
| 9684029 | Transmission line pulse and very fast transmission line pulse reflection control | Robert J. Gauthier, Jr., Evan Grund | 2017-06-20 |
| 9435841 | Integrated circuit protection during high-current ESD testing | James P. Di Sarro, Robert J. Gauthier, Jr., Nathan Jack, Souvick Mitra | 2016-09-06 |
| 9377496 | Cancellation of secondary reverse reflections in a very-fast transmission line pulse system | James P. Di Sarro, Robert J. Gauthier, Jr. | 2016-06-28 |
| 9274155 | Cancellation of secondary reverse reflections in a very-fast transmission line pulse system | James P. Di Sarro, Robert J. Gauthier, Jr. | 2016-03-01 |
| 8803276 | Electrostatic discharge (ESD) device and method of fabricating | Kiran V. Chatty, Robert J. Gauthier, Jr., Mujahid Muhammad | 2014-08-12 |
| 8796731 | Low leakage, low capacitance electrostatic discharge (ESD) silicon controlled recitifer (SCR), methods of manufacture and design structure | Michel J. Abou-Khalil, Kiran V. Chatty, Robert J. Gauthier, Jr., Junjun Li, Mujahid Muhammad | 2014-08-05 |
| 8760827 | Robust ESD protection circuit, method and design structure for tolerant and failsafe designs | John B. Campi, Jr., Kiran V. Chatty, Robert J. Gauthier, Jr., Junjun Li, Mujahid Muhammad | 2014-06-24 |
| 8730624 | Electrostatic discharge power clamp with a JFET based RC trigger circuit | Kiran V. Chatty, Robert J. Gauthier, Jr., Junjun Li, Rahul Mishra, Mujahid Muhammad | 2014-05-20 |
| 8634172 | Silicon controlled rectifier based electrostatic discharge protection circuit with integrated JFETs, method of operation and design structure | John B. Campi, Jr., Kiran V. Chatty, Robert J. Gauthier, Jr., Mujahid Muhammad | 2014-01-21 |
| 8614489 | Vertical NPNP structure in a triple well CMOS process | John B. Campi, Jr., Kiran V. Chatty, Robert J. Gauthier, Jr., Junjun Li, Rahul Mishra +1 more | 2013-12-24 |
| 8597993 | Electrostatic discharge (ESD) device and method of fabricating | Kiran V. Chatty, Robert J. Gauthier, Jr., Mujahid Muhammad | 2013-12-03 |
| 8513738 | ESD field-effect transistor and integrated diffusion resistor | John B. Campi, Jr., Kiran V. Chatty, Robert J. Gauthier, Jr., Junjun Li, Rahul Mishra +1 more | 2013-08-20 |
| 8363367 | Electrical overstress protection circuit | John B. Campi, Jr., Kiran V. Chatty, Robert J. Gauthier, Jr., Junjun Li, Mujahid Muhammad | 2013-01-29 |
| 8354722 | SCR/MOS clamp for ESD protection of integrated circuits | John B. Campi, Jr., Kiran V. Chatty, Robert J. Gauthier, Jr., Junjun Li, Rahul Mishra +1 more | 2013-01-15 |
| 8350329 | Low trigger voltage electrostatic discharge NFET in triple well CMOS technology | John B. Campi, Jr., Kiran V. Chatty, Robert J. Gauthier, Jr., Junjun Li, Rahul Mishra +1 more | 2013-01-08 |
| 8299533 | Vertical NPNP structure in a triple well CMOS process | John B. Campi, Jr., Kiran V. Chatty, Robert J. Gauthier, Jr., Junjun Li, Rahul Mishra +1 more | 2012-10-30 |
| 8169760 | Signal and power supply integrated ESD protection device | Kiran V. Chatty, Robert J. Gauthier, Jr., Mujahid Muhammad | 2012-05-01 |
| 7648869 | Method of fabricating semiconductor structures for latch-up suppression | Toshiharu Furukawa, Robert J. Gauthier, Jr., David V. Horak, Charles W. Koburger, III, Jack A. Mandelman +1 more | 2010-01-19 |
| 7385275 | Shallow trench isolation method for shielding trapped charge in a semiconductor device | Ethan H. Cannon, Toshiharu Furukawa, David V. Horak, Charles W. Koburger, III | 2008-06-10 |