Patent Leaderboard
USPTO Patent Rankings Data through Sept 30, 2025
MR

Mack W. Riley

IBM: 44 patents #2,042 of 70,183Top 3%
KTKabushiki Kaisha Toshiba: 1 patents #13,537 of 21,451Top 65%
Texas: #2,117 of 125,132 inventorsTop 2%
Overall (All Time): #68,044 of 4,157,543Top 2%
44 Patents All Time

Issued Patents All Time

Showing 26–44 of 44 patents

Patent #TitleCo-InventorsDate
7590194 Information handling system capable of detecting frequency lock of signals downstream from a signal synthesized by frequency synthesizer David William Boerstler, Matthew E. Fernsler, Eskinder Hailu, Jieming Qi 2009-09-15
7562272 Apparatus and method for using eFuses to store PLL configuration data Irene Beattie, Nathan P. Chelstrom, Matthew E. Fernsler 2009-07-14
7546504 System and method for advanced logic built-in self test with selection of scan channels Michael Fan Wang 2009-06-09
7516350 Dynamic frequency scaling sequence for multi-gigahertz microprocessors Nathan P. Chelstrom, Michael Fan Wang, Stephen Douglas Weitzel 2009-04-07
7512925 System and method for reducing test time for loading and executing an architecture verification program for a SoC Parag Birmiwal, Tilman Gloekler, Devi Shanmugam, Polisetty V. N. Srinivas 2009-03-31
7500164 Method for testing an integrated circuit device having elements with asynchronous clocks or dissimilar design methodologies Nathan P. Chelstrom, Steven R. Ferguson 2009-03-03
7496692 Validating chip configuration data Ingemar Holm, Ralph C. Koester, John Liberty 2009-02-24
7492793 Method for controlling asynchronous clock domains to perform synchronous operations Nathan P. Chelstrom 2009-02-17
7484153 Systems and methods for LBIST testing using isolatable scan chains Naoki Kiryu, Nathan P. Chelstrom 2009-01-27
7478300 Method for testing functional boundary logic at asynchronous clock boundaries of an integrated circuit device Nathan P. Chelstrom, Steven R. Ferguson 2009-01-13
7434127 eFuse programming data alignment verification apparatus and method 2008-10-07
7430264 Method to reduce transient current swings during mode transitions of high frequency/high power chips David William Boerstler, Eskinder Hailu, Michael Fan Wang 2008-09-30
7430624 High speed on-chip serial link apparatus and method Tilman Gloekler, Ingemar Holm, Ralph C. Koester 2008-09-30
7373573 Apparatus and method for using a single bank of eFuses to successively store testing data from multiple stages of testing 2008-05-13
7350096 Circuit to reduce power supply fluctuations in high frequency/ high power circuits David William Boerstler, Eskinder Hailu, Michael Fan Wang 2008-03-25
7308598 Algorithm to encode and compress array redundancy data Irene Beattie, Ingemar Holm 2007-12-11
7284138 Deep power saving by disabling clock distribution without separate clock distribution for power management logic Daniel Stasiak, Michael Fan Wang, Stephen Douglas Weitzel 2007-10-16
5301279 Apparatus for conditioning priority arbitration John Daniel Upton 1994-04-05
4691170 Frequency multiplier circuit 1987-09-01