Issued Patents All Time
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10354948 | Lossy MIM capacitor for on-die noise reduction | Chong Ding, Carl C. Hanke, Douglas Bruce White, Richard LaBarbera | 2019-07-16 |
| 7716516 | Method for controlling operation of microprocessor which performs duty cycle correction process | Yosuke Muraki, Tetsuji Tamura, Iwao Takiguchi, Makoto Aikawa, Eskinder Hailu +8 more | 2010-05-11 |
| 7702944 | Dynamic frequency scaling sequence for multi-gigahertz microprocessors | Nathan P. Chelstrom, Mack W. Riley, Michael Fan Wang | 2010-04-20 |
| 7698588 | Circuit and related method for synchronizing data signals to a core clock | David William Boerstler, Chulwoo Kim | 2010-04-13 |
| 7656237 | Method to gate off PLLS in a deep power saving state without separate clock distribution for power management logic | Mack W. Riley, Daniel Stasiak, Michael Fan Wang | 2010-02-02 |
| 7516350 | Dynamic frequency scaling sequence for multi-gigahertz microprocessors | Nathan P. Chelstrom, Mack W. Riley, Michael Fan Wang | 2009-04-07 |
| 7301385 | Methods and apparatus for managing clock skew | Chiaki Takano | 2007-11-27 |
| 7284138 | Deep power saving by disabling clock distribution without separate clock distribution for power management logic | Mack W. Riley, Daniel Stasiak, Michael Fan Wang | 2007-10-16 |
| 7262636 | Method and system for a circuit for timing sensitive applications | Toshihiko Himeno | 2007-08-28 |
| 6990165 | Phase and frequency lock detector | David William Boerstler | 2006-01-24 |
| 6914764 | On-chip thermal sensing circuit | Joachim Clabes, Ronald Nick Kalla | 2005-07-05 |
| 6792554 | Method and system for synchronously transferring data between clock domains sourced by the same clock | Gilles Gervais | 2004-09-14 |
| 6636980 | System for launching data on a bus by using first clock for alternately selecting data from two data streams and using second clock for launching data thereafter | Gilles Gervais, David George Caffo, James Nolan Hardage | 2003-10-21 |
| 6550013 | Memory clock generator and method therefor | Gilles Gervais, James D. Wagoner | 2003-04-15 |
| 5844921 | Method and apparatus for testing a hybrid circuit having macro and non-macro circuitry | Silvio E. Bou-Ghazale | 1998-12-01 |
| 5517650 | Bridge for a power managed computer system with multiple buses and system arbitration | Patrick M. Bland, Richard Gerard Hofmann, Dennis Moeller, Suksoon Yong, Moises Cases +1 more | 1996-05-14 |
| 5485127 | Integrated dynamic power dissipation control system for very large scale integrated (VLSI) chips | Renitia J. Bertoluzzi, Robert T. Jackson | 1996-01-16 |
| 4829198 | Fault tolerant logical circuitry | Gerald A. Maley, Joseph M. Mosley | 1989-05-09 |
| 4508981 | Driver circuitry for reducing on-chip Delta-I noise | Jack A. Dorler, Joseph M. Mosley | 1985-04-02 |
| 4417159 | Diode-transistor active pull up driver | Jack A. Dorler, Joseph M. Mosley, Richard O. Seeger | 1983-11-22 |
| 4383216 | AC Measurement means for use with power control means for eliminating circuit to circuit delay differences | Jack A. Dorler, Michael O. Jenkins, Joseph M. Mosley | 1983-05-10 |
| 4346343 | Power control means for eliminating circuit to circuit delay differences and providing a desired circuit delay | Erich Berndlmaier, Jack A. Dorler, Joseph M. Mosley | 1982-08-24 |