Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10268122 | Techniques to achieve area reduction through co-optimizing logic core blocks and memory redundancies | Abhik Ghosh, Niti Goel | 2019-04-23 |
| 10217732 | Techniques for forming a compacted array of functional cells | Rany T. Elsayed, Niti Goel, Randy J. Aksamit | 2019-02-26 |
| 10026686 | Decoupling capacitors and arrangements | Rany T. Elsayed, Niti Goel | 2018-07-17 |
| 7328415 | Modeling blocks of an integrated circuit for timing verification | Cuong Minh Le, Michael S. Jones, Timothy J. Fisher | 2008-02-05 |
| 5844921 | Method and apparatus for testing a hybrid circuit having macro and non-macro circuitry | Stephen Douglas Weitzel | 1998-12-01 |